Motorola 6800 verilog vhdl jobs

I need a vhdl project that integrates IoT and communications.

Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 through rules of the game are as follows: • After the first roll of the dice, the player wins if the sum is 7 or 11. The player loses if the sum is 2, 3, or 12. Otherwise, the sum the player obtained on the first roll is referred to as a reference point, and he or she must roll the dice again. • On the second or subsequent roll of the dice, the player wins if the sum equals the reference point, and he or she loses if...

Technology research is already done. Internal FPGA system architecture is already designed....designed. Therefore we only need you to implement and document it. Project is already split and documented as 10 milestones so that development can be done incrementally, step by step, and reviewed/monitored. Project is mostly Verilog development. Some simple programming necessary as well. Documentation is required. We expect you to reserve 10-20 hours per week for this project. It should be around 80 hours in total. We are interested in a quality implementation. If we are happy with it more projects will come in afterwards. We require you show some previous Verilog & documentation projects. Full project details, milestones and requirements will be shared once the candida...

I need single cycle 32 bit mips vhdl coding to find prime numbers. I will provide code to find prime number so you just have to build cpu for this specific purpose and I am also going to provide parameters for this architecture. I am gonna share project file after finalising with best person to do this job

We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado. There are 5 blocks in total with the following functionalities: 1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench. 2. RDM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench. 3. Clock-gen: Configure Xilinx PLL to generate the system clock and some divided clocks. Write testbench. 4. Latch block: Write a simple latch logic to control some outputs and testbench. 5. UART: Run verification on our IP with an existing testbench. More information available for suitable candidates upon request

I'm a electronic engineer and I have a good command on computer programs and also on digital programming like VHDL.

You have to write code and report for this .

In this project, you are required to develop a structural Floating-Point Unit (FPU) for use with a microprocessor. The processor needs to be capable of floating point addition and multiplication. The numbers are to be encoded into IEEE 754 single precision 32-bit format. The FPU sho...be able to detect and flag the 'NaN' cases. For the project demonstration, interface the FPU to the DE-10 RAM and perform the operation A*B+C on 1000 data triplets (A, B, C). Transfer the results back to the RAM, then upload to the PC for display. Verify the results by comparing them with another method (e.g., C program, spreadsheet etc.). This project Must be built using Quartus Prime's Verilog code. A code example is attached, you can follow the example but please modify it to fi...

I have the scheme of the project need only to work with the basys 3. Only to use buttons and switches from the basys3. Need the whole code in VHDL for Vivado.

We are looking for an experienced FPGA developer to write technical documentation related to Xilinx and Verilog development as well as custom hardware accelerators. Content is in the form of educational papers for semi-technical audience. Each article/paper is expected to be around 1900 words (4-5 pages, plus custom diagrams/infographics). Candidates must be able to prove experience in RTL/Verilog/FPGA development as well as previous articles/papers showcasing their proper grammar ability in the English language. Good dexterity in the English language is very important. Billing/invoicing/pricing is per article/paper. We will start with writing one article and if we are happy with the results we will continue writing further papers.

Hi, I'm looking for an experienced proofeditor to proof-read and to edit my 6800 words eBook. My budget is USD10. To apply, please send me your previous work samples — preferably with a "before editing" and "after editing" — or a document with "tracked changes" turned on, so I can evaluate your editing skills before hiring you. Thank you.

68000 assembly and C skills needed, also some basic hardware knowledge and embedded software development skills. The project is about low level game development on 1985 vintage hardware. Hardware is Motorola 68000 CPU and EF9366 Graphics Processor: Compiler is gcc: some low level harware routines need to be coded in m68k assembly. Therefore, m68k skills are essential, you need to be able to understand this: 000000e2 <__modsi3>: e2: 222f 0008 movel %sp@(8),%d1 e6: 202f 0004 movel %sp@(4),%d0 ea: 2f01 movel %d1,%sp@- ec: 2f00 movel %d0,%sp@- ee: 4eba ff40 jsr %pc@(30 <__divsi3>) f2: 508f addql #8,%sp f4: 222f 0008 movel %sp@(8),%d1 f8: 2f01

Has to be completed by the end of tomorrow (13/05/2019) Create VHDL code for chess clock, uploaded the task as a file.

Some work related to fpga and vhdl. Need any expert who can manage that

I have 2 schemes. One with neuron and with genetic algorithm. I need to combine both to train this neuron via genetic algo. Using VHDL in ISE design suite 14.7. Here is picture of two symbols that I want to combine(gen - genetic algorithm with build in neuron process, neur4sigm - neuron with sigmoid func). I need to train this neuron with this alforithm. You can modify inputs to 3 or 4 it's up to you. I want that this genetic algorithm train my neuron and return expected results(nout port inside gen). Also, For the future purposes I want that we can add not only one neuron but whole neural nets(ex: 3-4-1).

Want to be able to use accelerometer data on microblaze softcore processor, need SPI driver and interface on VHDL

Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from an electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relationship with the perfect electrical engineering freelancer. Thanks.

Hello, I'm currently working on a project that I am struggling with due to lack of VHDL experience. Want to create an SPI driver and interface it with a Microblaze softcore processor and the on-board accelerometer (ADXL362) so that the processor can read the accelerometer data.

Write system verilog codes to build a dual thread core processor working using Tomasulo algorithm. Please view the attached PDF for detailed information.

I need you to develop some VHDL software for me. Message for further details

I need you to develop some VHDL software for me. Contact me for more details

I have some simple VHDL tasks. My deadline is tomorrow. 1. Suggest a structural and behavioral description of a bidirectional cyclic shift register. 2. Suggest a structural and behavioral description of a bidirectional arithmetic shift register. Use parallel generation operators and configuration options. 3. Create a subroutine that performs the conversion between the integer and bit_vector types. Create an object and an architectural body to check this feature. 4. Create a package that declares one constant and one function, and its body. Save the package and its body in some library. Demonstrate the use of the library and use context statement operators to use the content of the package without a prefix. 5. Consider the following code: library ieee; use ; package config

VHDL and FPGA system details via PM

Design Verilog 32 bit adder, and use that to implement multiply using Xilinx

VHDL and FPGA system using vivado program.

I need you to develop some VHDL software for me. Must have good VHDL background. Message me for more details. Thank You.

I need a vhdl task done along with report

Looking for a Vivado Studio Specialist to evaluate code. On a Zturn board ( Xilinx Soc 7000 Series.) Skills required: AXI RTL Vhdl Vivado Studio

You have to complete coding and report writing

I want the verilog UART code along with pin assignment, synthesis and waveform outputs using Quartus II tool on ALTERA DE2 Board.

Smart phone repair and parts business. We sell parts for Motorola phone in India, Philippines, Malaysia and want to integrate logistics with my sales and inventory.I want a system with an integrated setup which manages each countries conversion rate and tax rate

I need a block to select some outputs based on the input and previous values of the input in VHDL

Product suggestions for a high volume/high demand (tens of thousands to hundreds of thousands) FPGA based consumer product using A3P series FPGA from Microsemi. Product must be easy-intermediate difficulty to design Verilog/VHDL and final manufacturing cost in $30-$50 as little other electronic components as possible. There is a possibility of design collaboration for winning entry.

Can Lenovo achieve competitive advantage in the global smartphone market? Case background: In October 2014, Chinese PC maker Lenovo completed the deal with Googleto acquire the Motorola Mobility smartphone businessfor US$2.91 the acquisition deal was completed, Motorola Mobility became Lenovo’s wholly owned subsidiary. Lenovo's CEO Yang Yuanqing stated that “The acquisition of such an iconic brand, innovative product portfolio and incredibly talented global team will immediately make Lenovo a strong global competitor in smartphone.” Assignment Question: To what extent do you think acquiring Motorola Mobility smartphone business canhelp Lenovo achieve competitive advantage in the global smartphone market?And why?

Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relation with the perfect electrical engineering freelancer. I need to hire 3 freelancers for 3 copies of the task. Thanks.

I need a random number generator which will work on a fpga board and the code should be written in xilinx, should be a vhdl code

I have the Deo Nano Soc and I want to read data using DMA. I need to read at a rate of about 2MB/s. I have used VHDL for a while and if you could provide some protocol/instructions at the top level, I could do the rest.

VHDL Project with registers for small business.

Starting a small business programming registers, buttons, and switches on my FPGA board in VHDL. Looking to hire a programmer that knows basic/simple vhdl coding skills and can complete the startup within a few days preferably.

A project to implement a calculator(ALU) in Verilog code using Quartus program I need a detailed report with state diagram and finite state machine I need one who can access my computer to teach me how to do the settings of the program also the Verilog code will be implemented on ALTERA board(DE2-115) also I need instructions of how I can run on the board (its due Saturday sharp)

Microprocessor design project using system verilog in Modelsim and physical validation on Quartus Prime. I have started writing code for some of the blocks. The Register file, ALU and Instruction memory are nearly complete. Assistance needed in writing the remainder of the blocks: the instruction register, the micro controller unit, the W register, the program counter and anything else needed to wire everything together. I would also appreciate comments within the design.

Hi I'm looking for a good vhdl programmer to help me with a code. I'm supposed to bring in a simple logo, then i,m supposed to be able to display the logo on the center of a screen(using a vga connection) and my name on the bottom left corner while being able to flip the logo with a button on my fpga board the deadline is thursday. thank you. I have the initial codes. I'll provide more details when we discuss

We are working on an FPGA based doppler flowmeter with a custom PCB. At the moment, we are in the process of modeling algorithms using raw data recording in Matlab. This freelancer will be tasked with coordinating with the DSP engineer to design and implement changes from the Matlab models into our custom PCB, which Cyclone IV based. There is an existing version of both the recording firmware and the production firmware; the freelancer will be responsible for learning these so that any changes can be made. Thanks!

Project requirements will be provided after talking.

I have a digital input measurement signal, 0 ~ 1.1V level. Each pulse is an event, that has a level HIGH width from 5ns to 10ns, and the minimum time between every 2 pulses' rising edges is 20ns. I need a system to histogram the time between all adjacent pulses' rising e...need from you: 1. A plan on what I need to buy to build this system. I have a ZCU102 board. So maybe something like AD9234-LF1000EBZ? Do let me know your plan in your proposal. 2. The deliverable is the firmware, including ZCU102 PL side RTL and bit file, Petalinux Image and drivers. 3. Remote support, to set up the whole system. 4. A block diagram and a brief explanation about your RTL code. Verilog is preferred. Please in the proposal, let me know how long would the project take and how much would ...

I need you to develop some software for me. I would like this software to be developed for Windows using Verilog/VHDL.

Create verilog code for an Alarm clock with testbenches. Alarm clock will display on 7 segment display. More information available upon request. Simple Project

Hi, I need some help on a Altera FPGA testcase. A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO. Written in Quartus 18.1 with Verilog/System Verilog. And a testbench for verification. The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read enable from data bus (active low) a chip enable (active low) for the data bus to be enabled for read/write and a pin that indicates FIFO has reached its 3/4 capacity. Inside the FPGA will be a single FIFO with 1024 words that data will be written to it via the 16bit bus and read again via the 16bit bus. FIFO will have 48bits word length. What is required is the complete Quartus project with source rtl files and a testbech t...

I am enclosing description in the files.

Verilog/System Verilog module to implement an FSM in the document that will be provided. The 7 segment display on the DE0-CV FPGA board will also be used to show its use. Document will be provided once discussed.