Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    237 jobs found, pricing in USD

    I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help

    $25 (Avg Bid)
    $25 Avg Bid
    5 bids

    I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card instead of normal RF or magnetic cards. How can a SW developer support me to develop SW to write on the Card and develop as well the back end server SW for verification and acknowledgment? No encryption required at this stage.

    $284 (Avg Bid)
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    4 bids

    translate c++ code in systemc and implement constrained random verification methodology.

    $44 (Avg Bid)
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    5 bids
    build a software 6 days left

    translate c++ code in systemc. and implement constrained random varification methodology.

    $20 (Avg Bid)
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    1 bids

    Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code.

    $188 (Avg Bid)
    $188 Avg Bid
    6 bids
    build a software 6 days left

    translate a C++ code in systemc module.

    $31 (Avg Bid)
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    3 bids

    you have to translate C++ code in systemc language.

    $33 (Avg Bid)
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    3 bids

    I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time required to do the job.

    $160 (Avg Bid)
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    10 bids

    more details will be given in the chat

    $18 (Avg Bid)
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    16 bids
    SoundLocator 5 days left

    Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position

    $598 (Avg Bid)
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    15 bids

    Здравствуйте, anandori! Я обратил внимание на ваш профиль и хотел бы предложить вам свой проект. Мы можем обсудить детали в чате.

    $50 (Avg Bid)
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    1 bids

    Serializer & Desrializer Implementation using ZC706 and MTX

    $29 / hr (Avg Bid)
    $29 / hr Avg Bid
    6 bids

    I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url removed, login to view] Please respond directly with any questions such as specific mining software and such.

    $2312 (Avg Bid)
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    8 bids
    Circuit at logism 5 days left
    VERIFIED

    implement a digital circuit in Logisim for a door lock.

    $25 (Avg Bid)
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    3 bids
    expert in vivado vhdl needed 4 days left
    VERIFIED

    expert in vivado and vhdl needed asap

    $25 (Avg Bid)
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    8 bids

    there should be A and B inputs and the circuit should check if the A is divisible by B or not. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b). we have only 30 minutes to do.

    $128 (Avg Bid)
    $128 Avg Bid
    7 bids
    digital circuit in logisim 4 days left
    VERIFIED

    we should draw a circuit in logisim. there should be 2 input like A and B. the circuit should check if A is dibisible by B or not. you should work with ALU. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b)

    $21 (Avg Bid)
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    4 bids

    I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this task by next Sunday, 22nd April before I started my a year placement in May.

    $46 (Avg Bid)
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    7 bids

    Given two 4-bit integers, A and B, build a circuit that can outputs 1 if A is divisible by B, or 0 otherwise. It should be done using 4 bit ALU

    $65 (Avg Bid)
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    8 bids

    using four bit ALU, given two numbers A and B we need to find if A is divisible by B

    $81 (Avg Bid)
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    14 bids