Verilog / VHDL jobs

Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Hire Verilog / VHDL Designers

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    10 jobs found, pricing in USD
    $17 / hr Avg Bid
    4 bids
    System Verilog Project 5 6 days left
    VERIFIED

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $132 (Avg Bid)
    $132 Avg Bid
    9 bids

    Hello, I need help with the modulation of my transceiver. I want to create a new header file with Wireless Development Suite and paste it into my library. Since I'm still relatively new to programming, I'm not sure what steps I need to take in this regard. To what extent, for example, something has to change in my own code.

    $157 (Avg Bid)
    $157 Avg Bid
    4 bids

    Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA

    $195 (Avg Bid)
    $195 Avg Bid
    4 bids
    FPGA Algorimths 3 days left
    VERIFIED

    FPGA Algorimths, harware, software

    $6068 (Avg Bid)
    $6068 Avg Bid
    7 bids
    OFDM System in MATLAB Project 2 days left
    VERIFIED

    I want a freelancer to do Matlab coding for OFDM System. These codes are also available online so freelancer can use the existing codes. I just want the below two simulations to work and get the output in Matlab. Simulation 1: Write Matlab code to Simulate OFDM system with different modulation scheme like (BPSK , QPSK and (16 , 64) QAM) and the transmitted signal pass through multipath Rayleigh channel (fast fading) which the channel has (multipath and its delay and its gain and the Doppler frequency). In the receiver, use adaptive algorithms (RLS , LMS and Bidirectional LMS) to estimate the channel and then detect the transmitted data. Simulation 2: Design normal OFDM system which include ordinary training sequence (pilot) in front of each block of data to be transmitted, with different modulation scheme like (BPSK , QPSK and (16 , 64) QAM) and the transmitted signal pass through multipath Rayleigh channel (fast fading) which the channel has (multipath and its delay and its gain and the Doppler frequency). In the receiver used ( RLS , LMS and Bidirectional LMS) adaptive algorithm to estimate the channel and then detect the transmitted data. All you need to do is to make the Matlab program to simulate both conditions and obtain the results in the form of graphs. The freelancer can use the existing available Matlab code and make a two .m files such as simulation1.m and simulation2.m

    $100 (Avg Bid)
    $100 Avg Bid
    10 bids

    MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function) 4. output of pid controller should be read on DAC (pmod DA4) [login to view URL] what is important is timing analysis ....for example how much time adc is taking to convert to digital should be realized and time taken by dac and time taken by fpga:

    $123 (Avg Bid)
    $123 Avg Bid
    11 bids

    control a sensorless bldc motor using fpga

    $19 / hr (Avg Bid)
    $19 / hr Avg Bid
    16 bids

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $133 (Avg Bid)
    $133 Avg Bid
    7 bids
    VHDL expert needed 2h left
    VERIFIED

    Expert in VHDL needed to work on a code

    $13 / hr (Avg Bid)
    $13 / hr Avg Bid
    16 bids