Mux testbench verilog jobs
I will provide a verilog code and what I need is just the simulation. You can use any software like xilinx etc. Finally, I need the power analysis (How much power is consumed)
develop a Verilog program that has the identical behavior as programmable digital delay timer
I want the verilog code according to the given document. I want the test bench code also. And i will program the code into the hardware i.e, i am using vivado tool in xlinx. It should satisfy all my requirements. And i also need the changes in the constraints file in order to develop on the development we are using the constraints file as arty.xdc. I am working on arty board.
i have fpga board xcs500e ,i need verilog code for any one kind of image processing ,verilog code for vga driver i.e. for input and output of image,ucf.m file for fpga kit mention above
Hello everyone, I need a project in Verilog for sending bits from PC to FPGA. And then the FPGA process the data and send it to a MCU. The output must be 1 bit/clock cycle. The idea is send the data using Matlab, so Matlab code would also be required. A clock signal and a load signal are also required. The load signal must be in high just only while the bits are being sent to the MCU and then goes to low level.
Hello everyone, I have a UART project in Verilog. What my project does is to receive 2 bytes and send again those 2 bytes This works perfectly. I want a testbench of my project and also I want to modify the project for sending/receiving 5 bytes instead of 2. I will provide you with the code.
I need to track object using particle filter algorithm. Just go through attached PDF. There are various steps. a) One step, Bhattacharya co-efficient calculation, needs square root and divider. I have those calculation. I have attached here too. b) I have attached MATLAB code to generate .coe or .tx...particle filter algorithm. Just go through attached PDF. There are various steps. a) One step, Bhattacharya co-efficient calculation, needs square root and divider. I have those calculation. I have attached here too. b) I have attached MATLAB code to generate .coe or .txt files of an image. Either image can be provided from testbench using text file or .coe file can be stored in BRAM. I need, 1. VHDL Code (Comments are compulsory) 2. VHDL Testbench 3....
we need to track an object where background keeps changing and plot its trajectory using FPGA. coding to be done on Verilog and interface with real-time data would be more helpful.
we need to track an object where background keeps changing and plot its trajectory using FPGA. coding to be done on Verilog and interface with real-time data would be more helpful.
Electronics Engineer - FPGA based designs We are looking for an experienced electronics design engineer who will be responsible for designing electronics boards mostly digital incorporating FPGA's for applic...of mechanical, fluids dynamics, physicists, software and engineers designing industrial ink jet printer systems using multiple ink jet technology platforms. You will be involved and/or be responsible for designing electronics circuits and boards incorporating FPGA's, coding, implementing and testing VHDL or verilog firmware associated with these future boards. You will also be involved or responsible for maintaining and adding features to an existing FPGA source code written in Verilog. Some projects involve the design of electronic circuitry to interface t...
need to identify position and velocity of an moving object using Kalman filter and optimize kalman filter for power using Verilog/HDL
Building a HEVC decoder and encoder using verilog for FPGA implementation.
hi i am saintlaw, I was talking to u about verilog coding and quartus project. I will be awarding you the project from this account because i had some money left in this account from a previous project. as we have agreed for 150 dollars to complete the project in 10 to 12 hours from now. please contact me in this account from now on. thank you.
Hi shobhitkapoor, i need one simple module in verilog written. do you think you can do it?
...Specification document (2) Verification Specification document (3) Verification Report document (4) Fitting Report and Timing (5) Timing constraints/fitting constraints/project files (6) Scripts for running test-benches (Cshell, Perl or tcl) (7) Scripts for running synthesis/map/par/image-file (8) Test-benches (System Verilog, Verilog or VHDL) (9) Test Vector files (10) Instructions how to run all the delivered scripts (10) RTL Code (System Verilog, Verilog or VHDL) (11) Interface description document (commands/registers/memory addresses etc) Host Computer SW Deliverables (1) Design Specification document (2) Matlab source code, functions and scripts in m-code (3) Example code how to use all the m-functions (4) Driver source code and proj...
I have the design almost finished but its not working correctly. I need the CPU to fetch and decode instructions such as Y = x^2 + 3 - 2 and store in Ram. Its 90% done I just cant seem to get it working.
Hi you have to create testbench for a 1X3 router with coverage coding. And you have to write SV assertions for a RAM memory.
Hardware used - Xilinx Nexys 4 FPGA Board - u-cam ii camera (communicates via UART to board) - Vivado softwar/verilog language The aim of this simple project is to implement colour tracking and display it on a monitor. Basically, the camera will detect (lets say red) coloured objects and when detected, a box/something be around it to show the user that it is detected. All this will be displayed to the monitor via VGA (the board has VGA connection)
The project must meet certain requirements. Firstly the project (VHDL design and VHDL testbench must be free of syntax errors. The VHDL project must synthesise with no problems, such as non-synthesisable code, latch inferred and multi-driver. Must show correct results from behavioural simulation and post-route simulation, in which the post-route delay can be observed. Must have the best coding quality with effective hardware resource consumed and efficient processing speed achieved. Must include notes on each section or line indicating processes and stages of code and what they are used for and how they are used.
Details attached. Please only bid after reading attached file. I will select most reasonable bid. Thanks
design an instruction memory module in verilog, Module is the part of the memory unit.
Hello everyone, I have a FPGA board connected to my PC through USB. This FPGA has a FTDI chip. I need to send data from Matlab to the FPGA and output this data to a pin, in order to see the data in a oscilloscope. The code must be written in Verilog.
I need a bash script in which i can restream video links example i have this link so i want to restream it via vlc or ffmpeg cvlc --sout='#http{mux=ts,dst=:8080/1}' so this command get and restream it to Also i need 1. Load balancing = if in server1 are connected example 100 user, 50 to redirect to server 2 and 50 to be on server1 job that will check if a stream goes down to restart it (restart the bash script) 3.(also u can put a .htaccess which will allow all visitors to watch videos just from my site (jw web player) and it need to allow some ip which can access m3u8 links from everywhere.(not just from mysite, Also allow only one connection per same ip).
I need a bash script in which i can restream video links example i have this link so i want to restream it via vlc or ffmpeg cvlc --sout='#http{mux=ts,dst=:8080/}' so this command get and restream it to Also i need 1. Load balancing = if in server1 are connected example 100 user, 50 to redirect to server 2 and 50 to be on server1 2. maybe we can put a .htaccess which will allow all visitors to watch videos just from my site (jw web player) and it need to allow some ip which can access m3u8 links from everywhere.(not just from mysite) 3. Cron job that will check if a stream goes down to restart it (restart the bash script)
I need a bash script in which i can restream video links example i have this link so i want to restream it via vlc or ffmpeg cvlc --sout='#http{mux=ts,dst=:8080/}' so this command get and restream it to Also i need 1. Load balancing = if in server1 are connected example 100 user, 50 to redirect to server 2 and 50 to be on server1 2. maybe we can put a .htaccess which will allow all visitors to watch videos just from my site (jw web player) and it need to allow some ip which can access m3u8 links from everywhere.(not just from mysite) 3. Cron job that will check if a stream goes down to restart it (restart the bash script)
I need a bash script in which i can restream video links example i have this link so i want to restream it via vlc or ffmpeg cvlc --sout='#http{mux=ts,dst=:8080/}' so this command get and restream it to Also i need 1. Load balancing = if in server1 are connected example 100 user, other users to be redirect to server2 or to if there are 100 users 50 to redirect to server 2 and 50 to be on server1 2. maybe we can put a .htaccess which will allow all visitors to watch videos just from my site (jw web player) and it need to allow some ip which can access m3u8 links from everywhere.(not just from mysite) 3. Cron job that will check if a stream goes down to restart
I need a bash script in which i can restream video links example i have this link so i want to restream it via vlc or ffmpeg cvlc --sout='#http{mux=ts,dst=:8080/}' so this command get and restream it to Also i need 1. Load balancing = if in server1 are connected example 100 user, other users to be redirect to another server 2. maybe we can put a .htaccess in mysite which will allow all visits from my site (jw web player) and it need to allow some ips which can access m3u8 link from everywhere.(not just from mysite) 3. Cron job that will check if a stream goes down to restart it (restart the bash script) 3.
So what i want is a detailed explanation (if some code showing in c/java some functions/constructor class which are implemented for the simulator's different functions as you mentioned in the explanation ) . Imagine i am telling this answer to a design automation engineer in an interview. So it should be a technical answer. Let me know if you have any concerns. Bid 20$ please for it
hello, i am in need of a verilog code for discrete wavelet transform. i will attach the papers i am working on. dwt paper is the dwt i need in my total project. i need it in 5days it is very small part of the project. thanks
i want to make a project on image steganography that is hiding text images in an image and i want to implement it on FPGA (field programmable gate array) using verilog. i want the whole source code and all the implementation steps and a full and final project report.
Router 1X3 using verilog and AHB_APB BRIDGE in verilog,fsm designing.
Implement an image face detection detection algorithm in FPGA using VHDL/ Verilog and also writing a MATLAB code to implement the same.
I am a final year student in my UG and my project is to read an image through verilog hdl without using matlab. I want to use gray scale coding in order to read the image and hence simulate by giving an image as an input and converting into bits which will later be given to matlab for verification of correct output. Will you accept it?
I am a final year student in my UG and my project is to read an image through verilog hdl without using matlab. I want to use gray scale coding in order to read the image and hence simulate by giving an image as an input and converting into bits which will later be given to matlab for verification of correct output. Will you accept it?
I am a final year student in my UG and my project is to read an image through verilog hdl without using matlab. I want to use gray scale coding in order to read the image and hence simulate by giving an image as an input and converting into bits which will later be given to matlab for verification of correct output. Will you accept it?
The project must meet certain requirements. Firstly the project (VHDL design and VHDL testbench must be free of syntax errors. The VHDL project must synthesise with no problems, such as non-synthesisable code, latch inferred and multi-driver. Must show correct results from behavioural simulation and post-route simulation, in which the post-route delay can be observed. Must have the best coding quality with effective hardware resource consumed and efficient processing speed achieved. Must include notes on each section or line indicating processes and stages of code and what they are used for and how they are used.
...comparator compares two 2-bit words, A and B, and assets outputs indicating whether the decimal equivalent of word A is less than, greater than or equal to that of word B. K-map method can be used to derive the minimized equations to describe the behavior of the comparator and Verilog module can be written to test the working of the comparator. Complete the following: o Derive minimized equations for the comparator outputs - A less than B, A equal to B, and A greater than B. Draw logic diagram. o Write and test the Verilog Module for this comparator. Provide detailed answers to the following: 1. How will you use a 3x8 decoder to build a 4x16 decoder? Draw a schematic diagram and explain your solution. 2. How will you use a 4x1 multiplexer to build a 16x1 multip...
I need two projects on VLSI design using verilog/vhdl language with complete coding and documentation.
Hi, I have a model file written in HSPICE and need to convert it into Verilog-A or Verilog-AMS. Thanks John
Hi, I have a model file written in HSPICE and need to convert it into Verilog-A or Verilog-AMS. Thanks John
...xyz’ b. ABC + A’B + ABC’ c. (x + y)’ (x’ + y’) 3. List the truth table of the following functions. Also draw the logic diagram (gate implementation of the following functions) a. F = xy + xy’ + y’z b. Y = (A + B) (C’ + D) 1. Write the canonical sum of products and canonical product of sums for the following functions: a. F = ΣX,Y,Z(0,3) b. F = ΠA,B,C(1,2,4) 2. Write Verilog code to describe the following functions: a. f1 = x1x3’ + x2x3’ + x3’x4’ + x1x2 +x1x4’ b. f2 = (x1 + x3’) . (x1 + x2 + x4’) . (x2 + x3’ + x4’) 3. A given system has 3 sensors that can produce an output of 0 or 1. The system operates properly when exactly one...
i have an fpga algorithm fully compatible for conversion to verilog. vhdl. i need some expert to define the acticture re assemble it and test it on fpga. i have some verilog implementation code for it too.
There was a phase 1 for this project it was designed and implemented using active HDL software, Verilog language. all we want is to convert the phase 1 design into magic software design (), the phase 1 is attached
I have complete Project code, It successful compile but its not showing any output, showing zero-zero. Please bid only if you are expert in Verilog.
