Verilog FLOATING POINT MULTIPLIER DESIGN BASED ON CSD (Canonical Sign Digit)

A proposal has not yet been provided

I have experiment in FP Multiplier Design, so you will get the well-written codes. Hope to make contact with you.

We have a team of expert and we can help you in doing your project such as writing, technical writing, Engineering, PCB designing, FPGA, Verilog /VHDL, MATLAB, Mathematics, Calculus, ETC. We are ready for hiring right now thanks.

I am a postgraduate in VLSI DESIGN and have worked on floating point multipliers during my research in masters. Proficient in using Xilinx and VHDL/verilog. Hope to have a conversation regarding this soon !!

This is my first Freelance project. Previously I have implemented AMBA APB bus , floating point ALU, asynchronous FIFO in verilog. After your offer I read many articles related to the floating point algorithm using CSD. If you have any specific design or paper which you want to implement then I am also ready for it then please send your design.