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MIPS Register File Design1

$250-750 USD

Closed
Posted over 9 years ago

$250-750 USD

Paid on delivery
in project 1, create separate VHDL files for the register, multiplexer, and decoder. Use also VHDL to instantiate them to build the register file. Instantiate the registers using a generate statement.
Project ID: 7044913

About the project

22 proposals
Remote project
Active 9 yrs ago

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22 freelancers are bidding on average $313 USD for this job
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Dear sir I read the document and I can do it perfectly I have more than 7 years experience in digital design using vhdl please contact me
$250 USD in 1 day
5.0 (284 reviews)
7.5
7.5
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Man! change the limits of you project! send me a message when you created the 111 USD project .
$250 USD in 0 day
5.0 (44 reviews)
5.8
5.8
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hi I am having good experience in VHDL and Verilog , I can acomplish the task in few hours only. I can also give some more discount if you are intrested then please do let me know. Thanks Shobhit
$250 USD in 10 days
4.8 (17 reviews)
4.5
4.5
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i have good experience working with MIPS single cycle and multi cycle processors,i am ready to complete the project
$263 USD in 10 days
5.0 (3 reviews)
4.1
4.1
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Hi I have very good experience in Verilog/VHDL coding. I have the coding available ready. Please ping me once your available. -- Thanks and Reagards Raja
$278 USD in 6 days
4.7 (8 reviews)
3.9
3.9
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A proposal has not yet been provided
$300 USD in 10 days
4.7 (4 reviews)
3.2
3.2
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A proposal has not yet been provided
$250 USD in 3 days
4.2 (1 review)
2.1
2.1
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A proposal has not yet been provided
$250 USD in 2 days
4.8 (2 reviews)
1.5
1.5
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Experienced Digital Design Engineer working on complex FPGA designs including DSP applications, high speed component interfacing etc. First hand industry experience in developing : 1) Synthesizable VHDL designs. 2) Designs that satisfy all timing constraints if any (via ucf file). 3) Designs optimized for both speed and resource usage. 4) Test benches for easy verification using ISIM. 5) Synthesizable test benches that can also be tested on hardware. 6) Easy to read source code with sufficient comments.
$250 USD in 2 days
0.0 (0 reviews)
0.0
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Propunerea nu a fost încă furnizată
$250 USD in 5 days
0.0 (0 reviews)
0.0
0.0
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I have done a smilar project and this won't be though to do at all. It would also help me since I'm a master student in computer engineering field.
$250 USD in 4 days
0.0 (0 reviews)
0.0
0.0
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i have more than 4 years of experience with vhdl so i believe that fit this project need. if you want you can check my profile and if you are interested srnd me pm to talk more
$833 USD in 20 days
0.0 (0 reviews)
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Hello, I can help you with this proyect becose I have a lot of experience in digital design. Greetings, Gabriel
$277 USD in 5 days
0.0 (0 reviews)
0.0
0.0
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Hello. My name is Milos Sapic and I am a Electronics engineer with experience in Digital desigen, i have experience with : Xilinx ISE, Active-HDL, Quartus II 13.0, Nios II 13.0, Qsys you can see in my portfolio. Please choose me and you will not regret and you will be satisfied with the speed and quality of work. I look forward to possible cooperation. Best regards Milos
$250 USD in 5 days
0.0 (0 reviews)
0.0
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I will do it for you with a price of 50$. Let me do it. I have much experiences on this easy project. Contact me soon.
$250 USD in 0 day
0.0 (0 reviews)
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Bis jetzt wurde noch kein Vorschlag eingegeben
$277 USD in 3 days
0.0 (0 reviews)
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A proposal has not yet been provided
$666 USD in 6 days
0.0 (0 reviews)
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Hi! I had experience in designing digital systems for dsp applications in fpga so i can do this well.
$250 USD in 10 days
0.0 (0 reviews)
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i have read and understand your requirement************* kindly open chat to proceed it further************************
$465 USD in 3 days
0.0 (0 reviews)
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I have been worked with vhdl more than 5 years, development of communications system, radar system, signal processing and others.
$250 USD in 5 days
0.0 (0 reviews)
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About the client

Flag of UNITED STATES
Sterling, United States
5.0
19
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Member since Jan 26, 2015

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