design and implemenatation of fft processor using vedic multiplier

I have had more than 3 years experiences on FPGA Design using Verilog and VHDL: - FPGA's Xilinx and Altera. - MicroBlaze, Embedded system design on FPGA of Xilinx. - FPGA, VLSI Implementation of DSP System( Matlab or C, C++, algorithm). - Digital logic design. - Some previous projects: + Matlab and FPGA Implementation of a License Plate Recognition System on FPGA Spartan-6 of Xilinx. + FPGA Implementation of a Fall Detection System on Virtex-5 Xilinx FPGA. + FPGA Implementation of a Fingerprint Identification System on Virtex-5 Xilinx FPGA. + VLSI Implementation of image/video compression in wavelet domain using DWT and SPIHT algorithm + Penalty football game on VGA DE2-70, DE2 Altera + AES 128, 256, 192. + MIPS Single-cycle, Pipeline processor.

Hello! I can help you right away! I have 10 years experience as a digital design engineer and vhdl/fpga implementer! Please send me a message to talk more about your project! Have a nice day!

Hi I have 10+ years of experience with VHDL/Verilog . previously I have designed vedic multiplier for my of client on freelancer , he gave me 5 star rating. I have also experience in FFT , I think I am suitable for this job ,please let me know how to take this further. Thanks SK

Hi We are experts in semiconductor domain. We understand your requirement and we have papers related the same topic. Looking forward to discuss with you and start the project immediately. -- Thanks and Regards Raja

Are you referring any IEEE paper for the same,pls share more information regarding your project,do you want simulation or synthesis or both

Hi, My Background: Manager, Designs. VHDL/Verilog/Algorithms expert. I've implemented the normal FFT (1024 point) in an FPGA for WiMAX 802.16D Communication system. Please send me details about your implementation for me to assist you better. Have a look at my profile for my complete work and portfolio for a few sample images. Feel free to ask any questions you have, i'll be happy to answer. Thanks for your time and consideration. Best Regards, Venkat

Experience on FIR Filters, FFT processor design and implementation,. Worked on FIR filter as LPF, HPF, BPF.

Hai, This is Anishkumar from your own contry. I am having total of 5 year experience in VHDL programming. I am also guided the students those done the projects in Vedic mathematics. So i will finish your project within the time line.

I am currently working on implementation of wavelet transform on FPGA. It required faster computation using vedic mathematics. Implimentation of FIR for FFT will be similar. I can deliver you the code within 7 days.

* Hand-on experience on Verilog through academic and industrial projects. * Good Understanding and Background in DSP and Signal Processing. * Currently working on low power microprocessor design with a module of vedic multiplier. * May also help in preparing presentation, report and posters. * Having support of Mentor and other academic staff. * Planning to pursue masters in VLSI and need to improve experience in such good projects. * Prioritize work over money. Freelancing to save for perusing masters.