fpga spi capture to serial in vhdl

Setup a fpga (ALTRA MAX3000A) or similar as an SPI slave and capture the channel frequency TX and RX data to a silicon systems si4464 by monitering MISO MOSI clock and Enable RX MOSI 0x77 followed by MISO up to 8 bytes containing the received data TX MOSI 0x66 followed by MOSI up to 8 bytes containing the Transmit data Frequency set MOSI 0x11 0x40 next byte is the number of bytes typically 0x08 followed by MOSI up to 8 bytes containing the Frequency data the FPGA is to filter the SPI stream and transmitt only these packets converted to text and each packet followed by a Carrage return Linefeed