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6095 - Developers in Xylinx - 30/04/2018 01:42 EDT

6095 - Developers in Xylinx - 30/04/2018 01:42 EDT

$30-250 USD

In Progress
Posted about 6 years ago

$30-250 USD

Paid on delivery
Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA
Electronics
Engineering
Verilog / VHDL
Project ID: 16830126

About the project

7 proposals
Remote project
Active 6 yrs ago

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7 freelancers are bidding on average $185 USD for this job
User Avatar
@ahmedmohamed85
Flag of EGYPT
A proposal has not yet been provided
$250 USD in 1 day
4.9 (395 reviews)
7.8
7.8
User Avatar
@prakashddit
Flag of INDIA
Expertise in Vivado and Xilinx FPGA
$77 USD in 1 day
4.8 (7 reviews)
3.6
3.6
User Avatar
@arunaupul
Flag of SRI LANKA
A proposal has not yet been provided
$166 USD in 5 days
4.6 (1 review)
2.5
2.5

About the client

Flag of INDIA
Delhi and Chennai, India
4.6
17
Payment method verified
Member since Feb 19, 2014

Client Verification

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