DMA for Xilinx Zynq

The project is to be performed on the Xilinx Zynq FPGA. Only the PL(Logic) needs to be developed. We need a DMA module that will take data from a predefined memory (of the ARM) and push it to a module implemented using AXI inside the FPGA fabric. As much of the available Xilinx IPs as possible(free versions) should be used. We need a sustained data rate of at least 300 Mbps. A test program that fills the memory with data can be provided by us or by the developer and will be used only for testing/verification. The data in memory will be divided into frames and the DMA should only read complete frames from memory. The interface between the DMA and the CPU should be decided by the developer, we just need it to work correctly. The result of the work should be a complete Vivado project. We will be testing it on a real ZedBoard (Zynq 7020). We will be glad to provide any additional needed information.