VLSI WITH VHDL or Verilog

Implement an SRAM circuit that has a 32 bytes with its associated decoder and multiplexer. The SRAM memory must have the following properties: 1- Addresses are from 0x8000 to 0x801F. 2- You can read and write one byte at a time. 3- The are special output signals that are required. They are listed in the table below. -------------- Requirement: Phase 1:Part 1: Verify the design using a logic design tool and an HDL tool (VHDL or Verilog) using structural method Part 2: List in a table the required components with their respective input and output labels. --- Phase 2: Part 3: Implement your design using Magic VLSI layout tool to generate your project layout [login to view URL] Part 4: Test your design using irsim to simulate your project. [login to view URL] phase 1 should be by Sunday Deliverables: TBD