Project using VHDL for FPGA

Completed Posted 5 years ago Paid on delivery
Completed Paid on delivery

Develop a musical bell that will play a selected and programmed song in the FPGA.

Implemented using the Vivado program on the Basys3 board.

FPGA Verilog / VHDL

Project ID: #17155645

About the project

4 proposals Remote project Active 5 years ago

Awarded to:

$88 USD in 1 day
(343 Reviews)
7.7