We are developing FPGA using Amazon AWS F1 service. The source code was converted from systemc to verilog using Vivado HLS. Many FPGA tool related issues needs to have an expert to help us. Including:
1) FPGA timing closure constraint
2) Place & route issues.
3) Set up clock divider to CL logic.
Potentially, we have a lot more work if you are familiar with Vivado HLS, and systemc.