In Progress

FPGA consultant on AWS F1

We are developing FPGA using Amazon AWS F1 service. The source code was converted from systemc to verilog using Vivado HLS. Many FPGA tool related issues needs to have an expert to help us. Including:

1) FPGA timing closure constraint

2) Place & route issues.

3) Set up clock divider to CL logic.

Potentially, we have a lot more work if you are familiar with Vivado HLS, and systemc.


Skills: Digital Design, FPGA, Verilog / VHDL

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About the Employer:
( 0 reviews ) United States

Project ID: #16472983

Awarded to:


Dear sir I have more than 10 years experience in digital design using FPGA, also I have implemented many projects using vivado hls, please message me so that we can discuss details Best regards Relevant Skills and Exp More

$52 USD / hour
(314 Reviews)

5 freelancers are bidding on average $53/hour for this job


Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a More

$50 USD / hour
(62 Reviews)

I have worked with many Xilinx FPGA products in the past 10 years. Have optimized designs to nearly fully utilize the FPGAs at use. I am well aware that this process is a multi dimensional optimization problem and with More

$60 USD / hour
(2 Reviews)
$50 USD / hour
(0 Reviews)

It's no suprise you run into timing problem,when you converter high level language (like system c) to [login to view URL] need some advanced skills to solve your [login to view URL] there're many skills to improve max clock frequency More

$55 USD / hour
(0 Reviews)