I'm an experience Verilog RTL developer in the SF bay area and looking to help you complete this project in a timely and accurate manner.
Please accept by bid, you will not be disappointed.
Relevant Skills and Experience
Verilog/VHDL, ADC converter, schematics, simulations using VCS, Xilinx, Altera, debugging skills, Chipscope, Modelsim
Proposed Milestones
$100 CAD - Initial review of problem and communication if there are questions
$50 CAD - Plan of work with block diagrams and proposed solutions
$50 CAD - Some pseudocode of Verilog and modules proposed
$342 CAD - Finish code work and verified functionality
Additional Services Offered
$200 CAD - Whatsapp or WeChat or Line chat help line after project
I'm a good communicater and task oriented. Will get the job done, working and in timely order.