system verilog, uvm, Script-- 3 -- 3

Hello! Please check my profile/reviews to know a bit about me. It would be great if I could help you out. Thank you!

Hi, I am an Accelerated Systems Engineer working on FPGA based digital systems designs. I have years of experience on RTL design based on Verilog HDL. I have project experience on advanced testing methodologies like system verilog constrained random testing based on UVM (Universal Verification Methodology). I would like to help you with your requirement Best Regards, Duvindu

Hi! I'm an electronic engineer I have experience working on ISE software and programming in verilog language. I'm open to what you need. Thank you.