VHDL - Programming Digital Design

€8-30 EUR

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about 5 years ago

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Digital Circuit will be represented and simulated via ModelSim simulator. Consider the digital circuit represented below. Two eight-bit wide data input ports are added. The result is then used to set one of eight output lines according to predefined thresholds. Code this design in VHDL and verify its correctness by writing a testbench. Simulate the design using the ModelSim simulator. What is the difference between the data type bit and the data type std_logic in VHDL? What is the difference between the data type bit_vector and the data type std_logic_vector in VHDL? What is the difference between VHDL signals and variables? Which data types are natively present in VHDL?

Electrical Engineering

Project ID: 18720927

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10 freelancers are bidding on average €26 EUR for this job

@ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using VHDL, please check my profile, also please message me so that we can discuss Best regards

€30 EUR in 1 day

4.9

(417 reviews)

7.8

@xaainulabideen

For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail. For more details inbox me so that we can discuss in detail.

€23 EUR in 1 day

4.8

(49 reviews)

5.8

@gaihrekrishna

Hello there, i am krishna [FPGA design engineer at LogicTronix]. I have good expertise with VHDL programming, FPGA Design and Embedded Design. Your questions answer [in short] The bit data type is used for such variable which can have only two states '1' or '0'. While the std_logic is used for the variable which can have more than two states value, std logic datatype can hold 9 different state values as '1'- high, '0'-low, 'X','Z'-high impedance, 'U'-undefined etc. And vector on the bit and std_logic is used to define the array type of variable. Signals are like as the jumpers or wires and variables are just the normal variable on other languages.

€28 EUR in 1 day

4.8

(1 review)

1.4

@asicdsm

Bit has only 2 values '0','1' std_logic has 9 values 'U','0','1','X','Z','-','H','L','W' Bit and bit_vector are natively present in VHDL. I assume that the inputs numbers are unsigned. Is it right ?

€34 EUR in 1 day

0.0

(0 reviews)

0.0

@tienthanhkt09

Hi there, I am interested in with this project. I'm familiar with the VHDL and Verilog design. Pls take a look in my profile. Thanks.

€29 EUR in 1 day

0.0

(0 reviews)

0.0

@eaglesofcoding

I made many vhdl projects both at work and at university. so your project is very easy . moreover if you are student i can do this freely dont hesitate to contact with me :)

€19 EUR in 1 day

0.0

(0 reviews)

0.0

@AdSamir

Hello, I believe I can get this task done as soon as possible (less than 1 day), with best optimizations and lowest cost! I can understand that this is educational task and that you are seeking informational help. I believe I am best suited for this task since I am a fresh graduate from the Digital Electronics course and I have the academic knowledge and educational way to offer the necessary help. Also, I love explaining and teaching. You can always comeback for more help whenever needed, with even much more lower costs! Looking forward for your reply. Best Regards, Adel.

€20 EUR in 1 day