In Progress

Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed.

Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed.

The bidder must use open source or free Viterbi decoders-Reed Solomon en/decoders-(De)Interleavers-Pseudorandom number generators (PRBS).

The Viterbi Decoder must be parameterizable (K=7, 1/2,3/4,7/8 puncturing etc.) and must support soft decision.

The Reed Solomon En/Decoder must be set to (223,255)

The Interleaver must be parameterizable

A Framer/Deframer must add/ remove Headers into the bitstream and should indicate a lock.

The Transmit Chain:

Data Source(PRBS)-> RS Encoder->Framer->Convolutional Coder-

The Receive Chain:

Viterbi decoder(soft decoding)->Deframer and Lock detection->RS decoding->PRBS Lock detection and BER Measurement

200 Mbps sustained decoding speed should me maintained.

Complete Simulation and HDL sources must be delivered.

The use of relevant Xilinx Evaluation cores are permitted.
All parameters should be set by registers.
It is a typical implementation of the standart TM SYNCHRONIZATION AND CHANNEL CODING which is located at The relevant sections are: Section 3,4,5,8,9 which deal with the Viterbi decoder, RS encoder/decoder, framing and scrambling and it is much more restricted as we gave the specific parameters for the Viterbi and RS decoder. The implementation is sometimes referred as NASA CCSDS.
A simple noise generator (or AWGN) can be added just for test purposes, the Input output can be 4-8 bits.

Skills: Electrical Engineering, Electronics, Microcontroller, Telecommunications Engineering, Verilog / VHDL

See more: kintex 7 product table, xilinx fpga selection guide, xilinx fpga comparison, xilinx reed solomon encoder, artix 7 pinout, artix 7 product table, ef-di-rse-site, spartan 7 product table, mysql error correction, qpsk error correction vhdl, http forbidden error correction, error correction php ajax, error correction oscommerce, error correction matlab, Error correction, movie error correction, reed solomon decoding codes, j2me calculator error correction, reed solomon student project, css error correction

About the Employer:
( 0 reviews ) ANKARA, Turkey

Project ID: #16491276

9 freelancers are bidding on average $691 for this job


A proposal has not yet been provided

$888 USD in 3 days
(365 Reviews)

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a More

$750 USD in 10 days
(72 Reviews)
$750 USD in 10 days
(22 Reviews)

Hello, My name is Mohamed. I have 5 years experience in digital design and FPGA. I checked your project description about implementing Reed Solomon Viterbi decoder on an ARTIX7-200T FPGA which support 200 Mbps. I ha More

$750 USD in 10 days
(71 Reviews)

I have extensive knowledge in digital design and Xilinx FPGAs, I hope working together, please contact over chat.

$750 USD in 20 days
(1 Review)

Hi, We will configure your Error correction Block (Viterbi+Reed Solomon) on ARTIX7-200T FPGA. Base on your description it appears that you are looking to build a receiver system similar to that for 802.11n/ac WiFi o More

$555 USD in 10 days
(8 Reviews)

Hello I have experience in FPGA communication projects. Bidding as per invite sent Happy to discuss and proceed. Thanks VJ

$722 USD in 20 days
(2 Reviews)

Dear Sir, I am expert on this work as you have mentioned on this website. Would you allow me to serve you with minimum price like $250 within 3days. Please let me know if you intend to award me the project. I could ass More

$277 USD in 3 days
(0 Reviews)

Hi, this task is much difficult to the former one (BPSK ,QPSK...) . here again, i give some vital modules, and its main function. Module: Branch Metrics,Add-Compare-Select, register exchange, Traceback . Brief Descri More

$777 USD in 10 days
(1 Review)