design and implemenatation of fft processor using vedic multiplier
₹12500-37500 INR
Paid on delivery
in this project we have to design fir filter and fft processor by using vedic mathematics
Project ID: #7107380
About the project
11 freelancers are bidding on average ₹17947 for this job
Hello! I can help you right away! I have 10 years experience as a digital design engineer and vhdl/fpga implementer! Please send me a message to talk more about your project! Have a nice day!
Hi I have 10+ years of experience with VHDL/Verilog . previously I have designed vedic multiplier for my of client on freelancer , he gave me 5 star rating. I have also experience in FFT , I think I am suitab More
Are you referring any IEEE paper for the same,pls share more information regarding your project,do you want simulation or synthesis or both
Hi, My Background: Manager, Designs. VHDL/Verilog/Algorithms expert. I've implemented the normal FFT (1024 point) in an FPGA for WiMAX 802.16D Communication system. Please send me details about your implementation More
Experience on FIR Filters, FFT processor design and implementation,. Worked on FIR filter as LPF, HPF, BPF.
Hai, This is Anishkumar from your own contry. I am having total of 5 year experience in VHDL programming. I am also guided the students those done the projects in Vedic mathematics. So i will finish your project withi More
I am currently working on implementation of wavelet transform on FPGA. It required faster computation using vedic mathematics. Implimentation of FIR for FFT will be similar. I can deliver you the code within 7 days.
* Hand-on experience on Verilog through academic and industrial projects. * Good Understanding and Background in DSP and Signal Processing. * Currently working on low power microprocessor design with a module of vedi More