UDP data filtering using Xilinx Zynq 7000 family Socs

Closed Posted 6 years ago Paid on delivery

$750-1500 USD

Paid on delivery

Closed Paid on delivery

UDP data filtering using Xilinx Zynq 7000 family Socs (10 Gb SFP+ port)

FPGA Verilog / VHDL

Project ID: #14600641

About the project

6 proposals Remote project Active 6 years ago

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6 freelancers are bidding on average $1204 for this job

ducdctoandh's Profile Picture
ducdctoandh

I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. Relevant Skills and Experience FPGA/VHDL/Verilog/Zynq Proposed Milestones More

$1500 USD in 20 days
(89 Reviews)
6.9
punamsengupta's Profile Picture
punamsengupta

A proposal has not yet been provided

$750 USD in 25 days
(13 Reviews)
3.8
kalshareef's Profile Picture
kalshareef

I have been working with ZYNQ FPGA for a while and I have a good understanding of the UDP protocol so I am confident that I can get the job done. Looking forward working with you. Relevant Skills and Experience Have b More

$1222 USD in 20 days
(0 Reviews)
0.0
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