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Design and test a VHDL model for the front end cluster of a speculative out-of-order 2-wide suerscalar processor.

$250-750 USD

Closed
Posted over 9 years ago

$250-750 USD

Paid on delivery
Design and test a VHDL model for the front end cluster of a speculative out-of-order 2-wide suerscalar processor. Assume the ISA specification provided in Moodle. Your submission should be a single file that contains the VHDL code of the front end cluster. This front end cluster should consist of 3 pipeline stages and 4 functional unit blocks (FUBs), as follows: 1. FUBs include: -8K byte direct map instruction cache. -4K entry direct map branch target buffer and bimodal predictor. -Decoder to generate pipeline control signals. -Register renaming unit to allocate buffer and register resources and to rename registers using the reorder buffer as physical register file. 2. Pipeline stages: - Stage 1 contains instruction cache and BTB/branch predictor. -Stage 2 contains the decoder. -Stage 3 contains the register renaming table and hardware to assign for each instruction a) a physical destination register in the reorder buffer, b) a reservation station, c) a load queue entry if an instruction is a load, and d) a store queue entry if the instruction is a store. Develop and test a VHDL model for the out-of-order execution and in-order commit sections of the superscalar CPU, including the reservation stations, execution units, reorder buffer and the register file. You should create one entity and one architecture for each unit and then connect them as components within an overall pipelined structural architecture. I. Reorder Buffer: Features include: 1. Functions as a queue of 32 entries. Implement the queue as a circular buffer with head pointer and tail pointer registers. Instructions are assigned entries at the tail and removed at the head. 2. four read ports to read valid bits and source operands for 2 instructions. 3. two write ports to write back two results, two valid bits, two branch mispredict bits and two exception bits for the destination registers of 2 instructions. 4. Status bits indicting when the reorder buffer is full or empty. 6. wrap-around toggle bit whenever the tail pointer changes from value 31 to value 0 as the tail pointer wraps around the circular ROB array. II. Reservation Stations: 1. Array of 16 reservation stations.. 3. Two dispatch ports, either one load/store instruction + branch/ALU instruction or two branch/ALU instructions. 4. Two write ports. 5. Two CAM ports to match tag and grab matching data from writeback buses. 6. Free list. This is an array that contains the IDs of the reservation stations that are not currently occupied. It is needed to assign reservation stations to instructions when they are written into the reservation stations. III. Execution Units: Two ALUs. IV. Register File: 1. 16 registers 2. 16 bits per register 3. 4 read ports to read 4 operands for 2 instructions in one cycle. 4. 2 write ports to retire 2 registers in one cycle.
Project ID: 6699114

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Active 9 yrs ago

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I'm an Expert in VHDL or Verilog as well as digital design with long time experience on this field. Now I'm working with it everyday as a researcher at SNU. Therefore, I can do it for you soon. We can discuss more about the deal. Thanks.
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can you discuss more details regarding the project, i have good experience with VHDl and verilog,worked with Xilinx and ALtera FPGA
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