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Design and implementation of MPEG-2 encoder on Altera FPGA

$350-750 USD

Closed
Posted over 8 years ago

$350-750 USD

Paid on delivery
Design an MPEG-2 encoder IP Core in Verilog or VHDL to compress a video signal resolution 640x480. The input images will be in the YCrCb color space. The IP core arquitecture should be Pipeline.
Project ID: 8376646

About the project

13 proposals
Remote project
Active 8 yrs ago

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13 freelancers are bidding on average $1,442 USD for this job
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Dear sir I have more than 8 years experience in digital design using vhdl and verilog please check my profile, I read the project requirements and I can do the required ip core, please message me so that we can discuss
$1,388 USD in 15 days
5.0 (313 reviews)
7.6
7.6
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A proposal has not yet been provided
$10,000 USD in 15 days
4.8 (99 reviews)
6.4
6.4
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Hi, I had done MS in Digital Systems Design and Image Processing. Also i had several years of experience in the field of FPGAs, VHDL and Verilog HDL. I had already worked on different image processing projects on FPGA like Fractal Image compression, etc. I can do this task for you
$1,333 USD in 10 days
4.8 (107 reviews)
6.2
6.2
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I would like to bid this job because I am really suitable for job description: First: I am an C++/C/Mathlab/Electronics engineer who is very familiar with C++/C/Mathlab/VHDL/Verilog. In fact, I have done so many project of C/C++VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird. Especialy, I participated image processoing project: a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Also,,I implemented the image conpression (wavelet transform). Besides, I have a Zedboard from Xilinx to verify the design. You need Altera FPGA, I have experience in that DE1, DE2. So if you want, I will implement in Zedboard first and I will transfer the desing to FPGA Xilinx. Finally, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers.. Please contact me and let me know if you want any special requirement. Thank you.
$555 USD in 15 days
4.9 (71 reviews)
5.9
5.9
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hi I have total 10+ years of experience in the MPEG and Video IPs , I have full proficiency in developing MPEG , Formatconverters , YUV convertors , YCrCb Convertors , this project sounds very suitable for me , and I can acomplish this in one month time frame. please let me know how to take this further. Thanks SK
$833 USD in 10 days
4.8 (18 reviews)
4.5
4.5
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A proposal has not yet been provided
$611 USD in 10 days
5.0 (18 reviews)
3.9
3.9
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I have been working with verilog more then one year. I have some ended projects on verilog, which work in hardware, not only in simulator. And a have been working with VHDL more then 3 years.
$444 USD in 7 days
0.0 (0 reviews)
0.0
0.0
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A proposal has not yet been provided
$611 USD in 15 days
0.0 (0 reviews)
0.0
0.0
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I am an accomplished Electronic & Telecommunication (E&T) Engineer with a comprehensive knowledge of designing integrated circuits and I have over 3-years experiences as implementing embedded systems on FPGA platform, processing digital signal (audio, image, video). I have also able to use hardware desciption languages: Verilog, VHDL, System Verilog; programming languages: C, C++, Assembly.
$500 USD in 12 days
0.0 (0 reviews)
0.0
0.0
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Hi , I can implement your application on a DE2-115 board and give you a demo as well . I have done several projects on image processing for FPGA 's . Regards , Ahmed
$443 USD in 30 days
0.0 (1 review)
0.0
0.0
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I have 20+ years of ASIC design experience with some FPGA experience as well. I will build the MPEG-2 encoder in verilog, verify it in simulation, and then implement using the Altera software.
$750 USD in 20 days
0.0 (0 reviews)
0.0
0.0
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I will be the best suited for this based on my experience in the domain. Earlier I worked on the Image processing stuff for LG.
$666 USD in 30 days
0.0 (0 reviews)
0.0
0.0

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Member since Sep 1, 2015

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