Vlsi verilog fpga asic jobs

This project will focus on the beam hash 2 algorithm . Using the fpga card by bittware cvp-13. I will need an optimized bitstream as well as a windows file.

this is a verilog project due may 30, i'll also need your help showing how the waveform display will work

There is a project to be done using edaplayground in verilog language. The aim of the project is to perform very simple CPU tasks. I can send samples and documents. It must be done until 7 May 2020. I have sample project. I can send.

There is a project to be done using edaplayground in verilog language. The aim of the project is to perform very simple CPU tasks. I can send samples and documents. It must be done until 7 May 2020. I have a sample project that works. I can send these.

Vending Machine Specification This specification is being developed for the St. Louis Lambda Lounge language shootout (May 2009). The goal is to create a specification specific enough for people to write semantically similar programs and ambiguous enough to allow people to solve the problem in a way idiomatic to the implementation language. The Problem The goal of this program is to model a vending machine and the state it must maintain during itʼs operation. How exactly the actions on the machine are driven is left intentionally vague and is up to the implementor. The machine works like all vending machines: it takes money then gives you stuff. The vending machine accepts money in the form of nickels, dimes, quarters, and paper dollars. Just for fun, letʼs leave the set of items being ven...

I have some real time inputs coming to FPGA via ADC . My objective is to process these inputs using mathematical expression and equations. For now i want to multiply and divide the inputs using fixed point and floating point techniques specially using inbuilt library. Also i want to apply square root and cube root operation over the inputs. If anyone is expert in mathematical computations using FPGA (VHDL only) please bid, only programming is expected.

I need only the software implementation, sorting core.h and sorting core.cpp. If you are expert, bid me

Experience with one of VHDL, HDL or Verilog languages Experience working with Xilinx FPGA and Vivado Hands-on with Audio/Video encoding/decoding Strong knowledge of x264 and x265 encoding Ability to use English well for work related Verbal and written communication

I have around 300 Bitmain Antminer s9 (ASICS) machines working with the platform awesome miner. I need an expert with the awesome miner platform and who knows how to: * Rules - Detect mining issues and automate tasks * Configure rules * Set up miners * Update Versions Many other things related to the awesome Miner administrative platform and the Antminer S9 (ASICS). Please a...machines working with the platform awesome miner. I need an expert with the awesome miner platform and who knows how to: * Rules - Detect mining issues and automate tasks * Configure rules * Set up miners * Update Versions Many other things related to the awesome Miner administrative platform and the Antminer S9 (ASICS). Please apply only if you have knowledge of this platform and the antminer s9 ASIC. ...

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Hello Shai! My understanding of fpga is not that great But what we need to do is implemenrat our trading strategy on fpga Implement* Strategy has 3 main components 1) Receive market data on UDP (which is GBs a second) and filet the data relevant to us 2) process the data filtered above and decide what orders to send 3) send the orders on TCP (and receive confirmations etc) Is this something that might be of interest to you and also if it sort of fits your skill set Thank you

Hi Ankita. My understanding of fpga is not that great But what we need to do is implemenrat our trading strategy on fpga Implement* Strategy has 3 main components 1) Receive market data on UDP (which is GBs a second) and filet the data relevant to us 2) process the data filtered above and decide what orders to send 3) send the orders on TCP (and receive confirmations etc) Is this something that might be of interest to you and also if it sort of fits your skill set Thank you

We are an hft firm based out of India and need to port our in-house software application to hardware

i have a project to do a coffee machine (using verilog) that the machine will let you choose for more than 3 drinks iced or hot drinks and if there is a change the machine will give it to you back , so it's like a vending machine , we want do it with a module and a state diagram and a block diagram , also we want to check if the simulation results is correct , thank you.

Need to create a PUF on FPGA for an academic project and generate challenge-response data set. Circuit to be implemented on FPGA is already there.

i have attached a picture i need you to implement QPSK in verilog

I need you to develop some software for me. I would like this software to be developed for Windows.

1. You have to teach us about RISC-V microcontroller architecture top to bottom and instructions . 2. You have to teach us about VHDL / VERILOG. 3. You can deal it with logisim software. 4. You have to give support and help us to build RISC-V microcontroller in FPGA. 5. You can take class about these minimum 2 days in online. 6. You will get 4 month to complete this. You will get 150$ as payment as a teacher. Payment can't be increased cause we are student(cause it is our saving money :) )

Need to do a few problems based on system verilog and simulations. I have some my own implemented files for most of the problems but they can’t work correctly. Need help with modifying my sv files based on the descriptions of homework problems. (HW description attached, I also have some supporting files and shell files to start with.)

Using your choice of programming language (Verilog, VHDL, C, C++, Python, Java), write a program which accepts half-, single-, or double-precision IEEE 754 floating-point binary operands and: Performs floating-point arithmetic (addition, multiplication).

The objectives of this project is to develop a two numbers 3-bit adder and then you must display the result using a 7-segment display in hexadecimal. 1. What type of G...using a 7-segment display in hexadecimal. 1. What type of GAL Chip you will use in this project? Sizes, input and output? (in Wincupl) 2. How many input and output needed in this project? 3. How many outputs for the 3 bit adder ? Write a WinCUPL code that would implement this project on a GAL device • Show the WinSim waveform simulation • Write a VHDL code that would implement this project on an FPGA device. • Show the VHDL simulated waveforms. • Write a report about your work. • Prepare and record a presentation that would explain how you did you work. • Answer the questions in the...

I’m trying to creat a verilog code

I need FPGA expert. feel free to apply thank you. I will provide details in chat

... I am looking for FPGA devloper to implement Forest Kitten VU33P Bitstream and miner for Grin Cuckatoo algorithm. Bitstream will likely have to be written from scratch but miner can be ported from one of open source GPU miners available. see information bellow on Target FPGA and algorithm. Link to Card Grin POW Info: grin miner - as miner plugin: Algorithm: Algo WhitePaper: Grin Implementation Cuckatoo (ASIC-targeted) Grin Mining Wiki: FPGA Description: https://cdn

Hi Loi L.,I noticed your profile and would like to talk about a project to develop a hardware security module in FPGA using Verilog. Design PCB might be also needed.

Hi Kulwant S.,I noticed your profile and would like to talk about a project to develop a hardware security module in FPGA using Verilog. Design PCB might be also needed.

Hi galenthas, I noticed your profile and would like to talk about a project to develop a hardware security module in FPGA using Verilog. Design PCB might be also needed.

Hi hungfreelancer, I noticed your profile and would like to talk about a project based on FPGA, Verilog and pcb design. We can discuss any details over chat.

Hi Ahmed N., I noticed your profile and would like to talk about a project based on FPGA, Verilog and pcb design.

I am researching the Travelling Salesman Problem and need to approach it in Python (preferably using Jupyter). Using data sets from here I need to approach TSP firstly with Linear Programming Solutions and then with Genetic Algorithms, for both small data sets as well as big ones in order to decide which of them (Linear Programming or GA's) offers a better solution.

I want to interface a Arducam (MT9V022 monochrome sensor) with a Nexys A7 board () and use the VGA port on the A7 to see what the camera sees on a VGA monitor. I want this done in Verilog (preferably on Vivado). I have a PCB board that maps the pins of the camera board () to three PMOD ports on the Nexys.

Verilog code Test bench

Hi. Previously you messaged me for a VLSI assignment. You need to solve 6 tasks in Cadence. Time: 36 hours You need to capture the screen recording during solving the problems and need to send me. Also, you need to send me the relevant files generated in Cadence I can pay you either by opening a new project here or paypal or any convenient way you want. We can adjust the price upon your skill. I need it for a task. Thanks.

Its a verilog project

Need a microprocessor must be written in system verilog.

For each of the following questions, first draw your design on paper. Then fill in the behavioral description in the attached Verilog and run it with the supplied testbench. Submit your designs (as a .pdf) and the modified Verilog file through Moodle. 1. Design an HLSM for a system with two single-bit inputs u and d each coming from a button and a 16-bit output C, which is initially 0. For each press of u, the system increments C. For each press of d, the system decrements C. If both buttons are pressed, the system does not change C. The system does not roll over; it goes no higher than the largest 16-bit unsigned integer and no lower than 0. A button press is detected as a change from 0 to 1; holding down a button does not count as multiple presses. 2. Design an HLSM for a s...

Tasks and scheduling Interruptions Race Direct access to peripherals

We have a requirement to do board IBIS simulation for 200 MHz DDR source-series termination memory channels. Please reach out for more information.

I am looking for expert Fpga cvp13 bistream developer

The next two questions require you to use Verilog to design and test larger datapaths. I have provided a library of structural descriptions of various components that you will be asked to use in your designs. Add your name to the top of this file and your code to the bottom. (a) Design a system that computes the sum of three 8-bit numbers. First build a behavioral description, then a structural description that uses one or more 8-bit adders from the library. Finally, write a testbench that tests both modules. (b) Design a system that computes the minimum of three 4-bit numbers. First build a behavioral description, then a structural description that uses components from the library. Finally, write a testbench that tests both modules.

I need an expert in VERILOG HDL DESIGN to do me a MINI PROJECT. it requires : -codes written -waveform

Implement the design using Magic VLSI layout tool to generate the project layout Test the design using irsim to simulate the project.

Consider a sorting circuit that accepts 8 numbers serially and outputs the sorted sequence serially. The sorting algorithm is the classic bubble sort algorithm. B. RTL Design Verilog Implementation :In Xilinx ISE software, implement your design in Verilog. c) Simulation waveforms for four (4) different input sequences (Part B).

-computer organization design 24 bit wide mips instruction. -The problem there is an error in the test so, we need results of the simulation -using verilog software

code development and report writing

I need this project for my master's program. Need LCD or any display controller Verilog files, test-benches, with a makefile, documentation, parent reference. That's will not be an old technology design, like a VGA controller.

Need research work on embedded & vlsi along with paper publication

Digital Integrated Circuits Design of 8-to-1 Multiplexer (MUX) using both cases of (1) only transmission gates (TG) and (2) other conventional CMOS gates. Compare the TG design with conventional CMOS gate designs by performance, power, chip size, number of transistors, etc. Electric VLSI Software needs to be used I need the file to do simulation on my computer LT SPICE and IRSIM For a report, put the following as a guide for your own design: 1) Draw logic symbol, schematic for simulation. 2) Draw stick diagram and Euler’s paths 3) Electric Schematic & Layout 4) LT SPICE and IRSIM where needed to show performance 5) Verify your design by putting pulses to see the outputs. 6) Complete a Truth table for the MUX. 7) Find a Boolean expression for the MUX. 8) Extract Rp, Rn...

FPGA Verification of my code using Fisher Algorithm

Hello, I need both PCB Design and Layout for a FPGA Project. The requirements are given below. The circuit will be a basic FPGA board with HDMI in and I/O pins out. We have choosen the FPGA and the other components. So you need to draw a schematic and make the layout.