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    3,364 vlsi verilog fpga asic jobs found, pricing in USD

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

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    I am looking at an FPGA project using xilinx the project has very specific functions that i do not have the skills required to implement it myself sadly so i hope you can help with that. The project is for a crypto miner that can mine using the cryptonote algorithm Variant 1 i have chosen a model of FPGA as it has 100k logic gates and good memory

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    Hello I am doing a small project and am on the lookout for FPGA and software developer to work on a prototype. We are creating a product that is very similar to SmallHD monitors where we take a HDMI signal, process that signal and display that video signal plus overlays such as histograms, false colour and 3D LUTS. What we require for this prototype

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    FPGA programming 4 days left

    I am in need of an FPGA programmer for a Xilinix FPGA which I plan to mine cryptocurrencies with. If you have knowledge in this field I hope to hear from you.

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    ...serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function)

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    ...serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function)

    $86 / hr (Avg Bid)
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    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

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    Hi, I want to implement a CNN in a Xilinx FPGA using Caffe or Tensorflow.

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    Hello, I have made a SAR 8 bits binairy coded ADC using method of 2 steps Successive Approximation, but it is a bit buggy. I need very experienced engineer in this field, otherwise it would just be loosing time. The simulation must be done in Cadence Virtuoso 6.x Thanks !

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    FPGA programming for mining 1 day left
    VERIFIED

    ...freelancer to develop FPGA software alghorithm for Cryptonight V7 mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. Develop FPGA bitstream for mining Cryptonight v7 (CN7) algorithm on Xilinx Virtex UltraScale+ FPGA VCU1525 card + modify the miner software on PC to communicate with the FPGA. Miner software can communicate with FPGA card either ...

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    Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA

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    Need someone to do circuit design for an FPGA board. The board is being made from scratch. All we have so far is the FPGA chip.

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    FPGA Algorimths, harware, software

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    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

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    MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function) 4. output of pid controller should be read on DAC

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    Looking for an experienced and ambitious programmer who has a keen interest in cryptocurrency algorithms and mining. Need a code to be programmed to enable a baikal N240 ASIC machine to be able to work on the new cryptonight light v7 algo...after the recent hardfork

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    ...you. This is what I'm looking for first. Coin Creation with block explorer. The coin I was hoping could be in PHP, anonymous (like Monero or Deep Onion), Proof of Work, and Asic and GPU resistance. Only CPUs can Mine this coin. How long do you think it will take you to finish that, and how much for the coin creation with the block explorer? Please

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    The PONF Project ([login to view URL]) want to create ...looking for an engineer that helps us design the electronics to control the Sony sensors to be connected to the Raspberry PI at the core of the project. We will be using Lattice FPGA to convert data. The requirement is to design the electronics, the relative PCB and create relative documentation.

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    Develop a musical bell that will play a selected and programmed song in the FPGA.

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    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

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    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

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    ...DE1-SoC developmental board and I need a template project which allows me to transfer about 2kB of settings from the HPS side to the FPGA side. I want to use C on the HPS side to set 2048x 8-bit values which the FPGA can use to synthesize an arbitrary waveform in real-time. The memory can be SDRAM or any other suitable options available on the DE1-SoC

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    control a sensorless bldc motor using fpga

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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

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    Mining Mining Mining Mining Mining Mining

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    I would like to hire a Firmware developer in C for FL256SAIF00 Asic chip via SPI driver to control a FLASH ASIC Chip. The driver must must be implemented as a-synchronized mechanism. The acceptance test will be passed with a application demo to play a memory array size from 0 - 32MB (write/read/erase) could work with sector or Bank address. Each time

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    I would like to hire a Firmware developer in C for FL256SAIF00 Asic chip via SPI driver to controll a FLASH ASIC Chip. The driver must must be implemented as a-synchronized mechanism. The acceptance test will be passed with a application demo to play a memory array size from 0 - 32MB (write/read/erase) could work with sector or Bank address. Each time

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    Looking for a embedded Linux developer/engineer for developing a driver for an iMX6 module on a custom board for capturing 16-bit greyscale video supplied by an FPGA through the camera sensor interface on the IPU of the microprocessor. Must have previous experience with IPU drivers and camera interfacing, as well as driver development for embedded Linux

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    ...tracking device for a specific application. I am seeking a solution that is an android and IOS application that is designed to track and locate a sensor (IOT, GPS, RF or other VLSI) technology that is embedded within a projectile that is no larger than 1.68-inches (42.7mm) in width, height and length. The IOS and Android applications should be able to

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    NDA
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    I want to parse a log file and use regexp to filter some patterns and put them in output log file. I have the script. 1- put the -p and -ig inside text files and feed it to code. like this: [login to view URL] -i [login to view URL] -o [login to view URL] -p [login to view URL] -ig [login to view URL] [login to view URL] is: warning| info [login to view URL] is: error| error: 2- in the [login to...

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    We are looking for a FPGA programmer, to build a mining software for Xilinx Virtex UltraScale+ FPGA VCU1525.

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    i am FPGA fan and , I try to setup connection between fpga device ( NetFPGA-1G-CML Kintex-7 ) and local computer . My main objective : simple comunication over ethernet cable . I have already done hardware design (in vivado) - microblaze core + TEMAC ([login to view URL]), which is verifed and works

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    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [login to view URL] Using PG236 [login to view URL]

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    ...amplifier (hence 6 amplifiers circuits). The output of the 6 amplifiers will go into 3 dual ADC's. The ADC will then send signal to connectors will an FPGA card will plug into. There is a signal from the FPGA that is sent to a DAC. I am basically designing a IO carrier board based on the ZED board (see attached) I can only work with US citizens since

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    In today's cryptocurrency mining sector there is a need for a fast and easy way to change mining pools and algorithms of mining on the ASIC. The solution is we offer one stratum where it will be possible to select multiple mining pools and switch between them from anywhere with an online connectivity. There is already a github project to begin with

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    1. Create a top level VHDL file for the project. VHDL code should be well formatted and commented. 2. Add two instantiations of a sync counter to the top level that are customized for the horizontal and vertical sync signals 3. Adapt the tesbench from homework 2 to simulate the top level file. Simulations should be annotated to depict events important to the operation of the design

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    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

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    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

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    I need image encryption using verilog on FPGA board

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    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

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    Develop and deliver FPGA code in vivado to: Take in attached NOAA wave file (IQ based) and decode it into a weather satellite image. This wave file was a recording of from NOAA satellite's Automatic Picture Transmission. The signal itself is a 256-level amplitude modulated 2400Hz subcarrier, which is then frequency modulated onto the 137 MHz-band

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    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

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    RISC processor using FPGA

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    RISC processor on FPGA

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    Designing of a pipeline processor which uses RISC like instruction set And implementation on fpga

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    "Need FPGA implementation of a Radar Matched Filter using Xilinx FPGA "

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    Altera FPGA DMA PCIe Ended
    VERIFIED

    I am looking for FPGA designer (Altera) with experience in DMA over PCIe.

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    Required skills : Electronics, VLSI, Autocad design, electrical circuits , circuit design Dear Freelancer, Need to create a 3D animation format about 1) How the computer wirless mouse works including inner electronics ciruits. 2) Inner and outer layer 3) Signal processing (laser) and sensing including mouse dpi 4) On/Off switch 5) Internal battery

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    vhdl code for wireless adhoc network and its implementation in FPGA,

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