Vlsi verilog fpga asic jobs

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    3,167 vlsi verilog fpga asic jobs found, pricing in USD

    design an Sdram ddr using verilog and test, verify it using Synopsis and TETRAMAX ATPG. finally verify the same design in FPGA.

    $333 (Avg Bid)
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    Hi Anh I need you to help with an image processing work to be implemented in FPGA. I have done its sample simulation in matlab. can you be of assistance? Thanks Mike

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    Hi Quan I need you to help with an image processing work to be implemented in FPGA. I have done its sample simulation in matlab. can you be of assistance? Thanks Mike

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    Hi. I've got an advanced FPGA and ARM PCB design that currently works, but I'd like it improved since we have signal integrity issues at the moment and would like a much nicer re-designed board layout. Thanks.

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    Tell me what you can do to make me an FPGA miner. This is just a paid discussion you don't have to do any work yet. If you can do something for me then we can move forward. Thanks.

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    Hi. I've got an advanced FPGA and ARM PCB design that currently works, but I'd like it improved since we have signal integrity issues at the moment and would like a much nicer re-designed board layout. Thanks.

    $819 (Avg Bid)
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    25 bids

    ...Option to connect to other mining pools. 4. Options to adjust intensity, work size, threads, and other possible settings. 5. Need AMD and NVidia GPU support. 6. Possibly offer ASIC support although this is not yet certain. 7. Windows and Linux support. 8. GUI or CLI for windows client is optional depending on pricing. Please let me know what quotes

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    looking for someone who can write a code to parse below code(using pyparsing) immediately : module module-name(input a, input b, input c, output r); wire mid1; mid1=a&(~b) wire mid2=b|c; wire mid3=a|c,mid4=b&c; wire mid5,mid6; mid5=a|(~c); mid6=a&b; r=mid5|mid6 endmodule *we have 4 ways to define wire as shown in above exampl...

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    Hi olegkaravaev84, I need you to help with an image processing work to be implemented in FPGA. I have done its sample simulation in matlab. can you be of assistance? Thanks Mike

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    Hi Umair I need you to help with an image processing work to be implemented in FPGA. I have done its sample simulation in matlab. can you be of assistance? Thanks Mike

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    Hi Kareem I need you to help with an image processing work to be implemented in FPGA. I have done its sample simulation in matlab. can you be of assistance? Thanks Mike

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    Hi Zain I need you to help with an image processing work to be implemented in FPGA. I have done its sample simulation in matlab. can you be of assistance? Thanks Mike

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    I want someone who can help me to read the results data from FPGA board on MATLAB software. Verilog HDL language will be used.

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    Hi Chhanda, I need you to help with an image processing work to be implemented in FPGA. I have done its sample simulation in matlab. can you be of assistance? Thanks Mike

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    heyo! im in...will likely never be profitable but im on a mission, im running a macinsosh full node of btc; i want to open the appropriate port --modem config; config for use of my usb asic devices for mining on macintosh maybe with macminer; and commence to mine my node solo; I would like someone to either guide me virtually or assist in person.

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    The person will need to have experience and be competent in assembly, install, software/hardware interfaces for ASIC mining devices as well as (this is not as iimportant as the ASIC experience/expertise), GPU Graphic card mining rig upkeep, hardware/software interface set up, and ongoing maintenance for all of the above. The person will need to be

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    need some help with verilog code.

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    I'm building a license plate detection system,...using MATLAB. The current challenge is to implement the design on an Altera DE Board FPGA using VHDL. At this point, because of time constraints I like to ask for ur assistance in the following areas I seek someone who could help Implement the design on an FPGA. Attached is the matlab code

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    Code for a specific signal passing through some noise being received on the other side. Complete with testbench

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    This is the project: FSM, saving data blocks received via RS-232 with fixed baud rate in external RAM and extracting necessary byte from arbitrary address (selected by slide-switches). - I need VHDL code and Testbench. -Explain its behavior and parts. I am using ZedBoard ZYNQ SOC training , Xilinx Zynq-7000

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