Vlsi verilog fpga asic jobs

Filter

My recent searches
Filter by:
Budget
to
to
to
Type
Skills
Languages
    Job State
    3,597 vlsi verilog fpga asic jobs found, pricing in USD
    Animated video 6 days left

    Compare renewable energy sources: a.) Solar b.) Wind c.) Hydro d.) Geothermal Show the cost of producing electr...same as the previous diagram The point we are trying to make here is that geo is perfect for mining because the energy is available all the time. PS: It's a good idea to show ASIC miners or mining rig while showing the mining operation.

    $452 (Avg Bid)
    $452 Avg Bid
    34 bids

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

    $114 (Avg Bid)
    $114 Avg Bid
    6 bids

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

    $142 (Avg Bid)
    $142 Avg Bid
    5 bids

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    $140 (Avg Bid)
    $140 Avg Bid
    1 bids

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) Look at the problems in: [login to view URL] WILL PAY GENEROUSLY. $$$ Project Description is: [login to view URL] Reference Literature: CMOS VLSI Design Happy Bidding

    $10 - $200
    $10 - $200
    0 bids

    VHDL implemented in altera de2 board

    $430 (Avg Bid)
    $430 Avg Bid
    4 bids

    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

    $17 (Avg Bid)
    $17 Avg Bid
    2 bids

    Responsibilities: 1. Engaged in ARM embedded software development (zynq7000 platform development); 2. Debugging WiFi driver and USB driver 3. Build and compile the ke... Build and compile the kernel driver environment 4. Realize the interaction between PS and PL 5. Porting algorithms to embedded platforms (including but not limited to ARM, FPGA, etc.)

    $2437 (Avg Bid)
    $2437 Avg Bid
    16 bids

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) MUST BE ACCURATE AND CORRECT. WILL PAY GENEROUSLY. $$$ Project Description is: [login to view URL] Reference Literature: CMOS VLSI Design Happy Bidding

    $275 (Avg Bid)
    $275 Avg Bid
    2 bids

    Simple CMOS VLSI Design Project (Power, Sequential Timing, Logic Families, Wires & Memory) MUST BE ACCURATE AND CORRECT. WILL PAY GENEROUSLY. $$$ Project Description is: [login to view URL] Reference Literature: CMOS VLSI Design Happy Bidding

    $155 (Avg Bid)
    $155 Avg Bid
    1 bids

    ...guidelines for the following professional boards: - Accounting Professionals & Ethical Standards Board (APESB) (11 x documents) - Australian Securities & Investments Commission (ASIC) (1 x document) - Australian Taxation Office (ATO) (2 x documents) - Chartered Professional Accountants (CPA) (4 x documents) - Office of Australian Information Commissioner

    $120 (Avg Bid)
    $120 Avg Bid
    5 bids

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    $88 (Avg Bid)
    $88 Avg Bid
    5 bids

    Verilog simulation of two action-reaction processes

    $29 (Avg Bid)
    $29 Avg Bid
    6 bids

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    $178 (Avg Bid)
    $178 Avg Bid
    7 bids

    ...deconding and encoding. this will be run on an MyRIO unit so should either be written for this or easily ported from another DAQ system. Ideally it would utilise the RT Module and FPGA Module and operate with as little overhead as possible. The VI should be able the, in terms of the decoder, output a string or timestamp with the current real time LTC timecode

    $345 (Avg Bid)
    $345 Avg Bid
    5 bids

    How does the parking system work? The p...that i am authorized to park only at level 2 and there is only for example 7 vacant lots for staff in level 2. The system is : FPGA ;Nexys 2 spartan 3E, Camera connected to the FPGA, And the monitor connected via VGA to the FPGA, The gates(pairs of IR sensors) in a bread board as illustrated in the abstract.

    $766 (Avg Bid)
    $766 Avg Bid
    3 bids

    Need help program FPGA with Artix-7 using Verliog.

    $125 (Avg Bid)
    $125 Avg Bid
    5 bids
    $20 / hr Avg Bid
    3 bids

    ARM firmware with LINUX for DE10-Nano board A. Play with the evaluation board 1. Project Owner will provide a P0496 ARM Processor base on Cyclone V SE FPGA computer board (DE10-Nano board). The board will have Ethernet port and SD card. 2. Developer needs to prepare LINUX Kernel to run on embedded computer board with Ethernet TCP/IP to connect with

    $4046 (Avg Bid)
    $4046 Avg Bid
    21 bids

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    $175 (Avg Bid)
    $175 Avg Bid
    1 bids

    Implement the Zen Protocol in the FPGA and update the Mining App

    $1220 (Avg Bid)
    $1220 Avg Bid
    3 bids

    ...but you also have to write the result to the $rd register as R-type instructions require. Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed except for the register module. This means you cannot use assign, ifelse, always, ?: and etc

    $27 (Avg Bid)
    $27 Avg Bid
    2 bids

    I have a Introduction to VLSI Design school course project. I have done most of topics but need to ask a questions and bugs about the project. Need someone to help on this very basic project. Freelancer should known the base sturecture of VLSI lecture. Freelancer either can be student, graduat, postgraduate or more.

    $42 (Avg Bid)
    $42 Avg Bid
    8 bids

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    $529 (Avg Bid)
    $529 Avg Bid
    15 bids

    questions on Hardware Design Language and Programmable Logic Regarding Verilog or System Verilog questions. - Writing a function / typdef struct /identifing the types of errors, ... - (pulse width modulation, frequency dividers, counters, sorting, generating a sequence like a Fibonacci sequence, finite state machine, test benches, math functions

    $25 (Avg Bid)
    $25 Avg Bid
    6 bids

    Make a serial interface system using Verilog

    $48 (Avg Bid)
    $48 Avg Bid
    4 bids

    Use a Verilog and Do exactly what is on the paper and hand me a report with codes, synthesized diagrams, and a description comparing the different state assignments

    $24 (Avg Bid)
    $24 Avg Bid
    7 bids

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

    $56 (Avg Bid)
    $56 Avg Bid
    14 bids

    We have an in-house trading application which we intend to move to FPGA, using metamako or solarflare fdk

    $80 / hr (Avg Bid)
    $80 / hr Avg Bid
    1 bids

    Its a small assignment. If you are an expert and have worked on it before. text me

    $129 (Avg Bid)
    $129 Avg Bid
    9 bids

    Hi TIV LAbs, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Have you worked on the nexys 4 ddr fpga board?

    $37 (Avg Bid)
    $37 Avg Bid
    1 bids

    ...but you also have to write the result to the $rd register as R-type instructions require. Write a structural Verilog on Altera Quartus II tool to implement a 32-bit R-type MIPS. Only structural Verilog is allowed, dataflow and behavioral Verilog is not allowed except for the register module. This means you cannot use assign, ifelse, always, ?: and etc

    $28 (Avg Bid)
    $28 Avg Bid
    5 bids

    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with

    $2299 (Avg Bid)
    $2299 Avg Bid
    10 bids

    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the play...demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

    $372 (Avg Bid)
    Featured
    $372 Avg Bid
    3 bids

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

    $186 (Avg Bid)
    $186 Avg Bid
    8 bids

    Business Card needs to be designed wi...Payroll processing - Daily bookkeeping - GST, BAS & IAS - Liaising with the ATO - Financial statements - Tax Returns - Annual tax planning - Performance reporting - ASIC compliance - Xero, MYOB, and Quickbooks Set-up and Training - Business Start-up and Structuring Tag Line- Get The Success You Need

    $18 (Avg Bid)
    Guaranteed
    $18
    154 entries

    1. Design platform: VIVADO 18.2 2. Chip: xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 channel bit width

    $150 (Avg Bid)
    $150 Avg Bid
    6 bids

    Need to Build the FPGA to HPS DMA code in Arria 10 Intel-Altera FPGA

    $392 (Avg Bid)
    $392 Avg Bid
    2 bids

    fpga pattern generator connected to a pc starting from an evaluation board and an HDL from TI.

    $305 (Avg Bid)
    $305 Avg Bid
    8 bids

    Design of a signal generator using verilog hdl. Should be done using Vivado Design Suite . More details in chat.

    $27 (Avg Bid)
    $27 Avg Bid
    6 bids

    i have some work related to VLSI and i need someone who can do it in efficient way. Should have good command in designing logic circuit designs. should have good knowledge of CMOS, NMOS transistors etc.

    $27 (Avg Bid)
    $27 Avg Bid
    9 bids

    I need to perform video compression using FPGA My final aim is to get a .bit or to .bin file so that I can burn the image to my fpga and simply voila.. Kindly visit this link in order to get an insight to the board that I will be using… [login to view URL] I want video to

    $158 (Avg Bid)
    $158 Avg Bid
    4 bids

    I have my FPGA Xilinx Artix 7 XC7A50T development platform for my personal project. It has DDR3, Hi-speed ADC, Hi-speed DAC, UART, SPI(x2), IIC, and an Ethernet MAC. I need a complete design with microBlaze. I can provide a small example xpr prj but not yet finished. I need someone to configure and link the ip together and have it finally synthesis

    $188 (Avg Bid)
    $188 Avg Bid
    9 bids

    Need a vhdl expert for Vhdl Code modification. Clock divider and counter design. Code needs to be run on an fpga. Thanks

    $22 (Avg Bid)
    $22 Avg Bid
    12 bids

    I'm trying to port PYNQ over to a diligent board that is not directly supported. I'm hoping somebody has already done this that would be willing to share their SD card files with me to save me the trouble. I'm looking for PYNQ version 2.2 or 2.3. Please and thankyou.

    $143 (Avg Bid)
    $143 Avg Bid
    3 bids

    image watermarking baed on dct algorithm in verilog code, need to implement in xilinx board

    $219 (Avg Bid)
    $219 Avg Bid
    4 bids

    Part 1: Dynamic Patterns Using LEDs Requirement In this part, you are required to write a Verilog code that produces at least four different dynamic patterns, that is changing with time with reasonable speed. And those patterns are controlled by switches. Features • Use the most left switches to change the patterns. • Design your own patterns. • Use

    $137 (Avg Bid)
    $137 Avg Bid
    8 bids