I am a co-founder of Verifast Technologies. We were in process of building online simulation tool for ASIC development. Base code is ready and seen demo, but after that development team decided to drop the project and send me just code base. This project includes: - Take the code base and make it live on [url removed, login to view] - Add user authentication access
Synchronous control of 8 stepping motors with calculation of a trajectory of linear motion and circular motion with constant acceleration for CNC machine. SystemVerilog, FPGA Altera (IntelFPGA)
...Grafik soll der "Bitpower" (unser Produkt) bildlich veranschaulicht werden. Der Bitpower setzt sich zusammen aus ... - GPU Altcoin (Scrypt-N, Equihash) - ASIC Altcoin (Scrypt, X11, X13, X14, X15) - ASIC Bitcoin & Bitcoin Cash (SHA-256) ...dies sind auch die Daten welche in der Grafik beschrieben werden soll. Diese verschiedenen Technologien nutzen wir
I need someone who is expert in academic writing and EE engineering communication and radar field and also embedded systems FPGA, the page's number will be around 50, and the topic and results and design are ready just need to be written.
Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed. The bidder must use open source or free Viterbi decoders-Reed Solomon en/decoders-(De)Interleavers-Pseudorandom number generators (PRBS). The Viterbi Decoder must be parameterizable (K=7, 1/2,3/4,7/8 puncturing etc.) and must support
A (PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. This project is a mere test for the abilities of the bidder. Several Add-On projects will follow. An PSK (BPSK, QPSK, OQPSK, 8-PSK) modulator/ demodulator for the ARTIX7-200 platform is needed. The PSK modulator must have a sampling rate selection between 1ksps-400 MSPS, The PSK demodulator must have a sampling rate selec...
...modify existing drivers based on Java to communicate with a FPGA based Bill validator from a Raspberry pi over USB. We previously modified existing java files to communicate with a bill validator that we later found out was using an old PSD based chip, whereas the new devices are based on FPGA chips. Our old code does not communicate with these newer
A S type stepper motor controller in verilog. It will take no of steps and frequency as input from ARM MC and generate PWM signal as ouput .
We are developing FPGA using Amazon AWS F1 service. The source code was converted from systemc to verilog using Vivado HLS. Many FPGA tool related issues needs to have an expert to help us. Including: 1) FPGA timing closure constraint 2) Place & route issues. 3) Set up clock divider to CL logic. Potentially, we have a lot more work if you
I need a Stepper motor controller code in verilog, the controller should take Frequency, direction and number of steps as an input and generate a S shape signal for Driver IC , based on that signal the driver IC will control the stepper motor .
...source code which can compile qt wallets and [url removed, login to view],the mining algorithm (scrypt) is wrongly chosen and a few ASIC miners quickly dominate the mining and make all other GPU miners unable to [url removed, login to view] to change the algorithm to a ASIC resistant one (e.g. Equihash,Timetravel 10 or something suggested by programmer ).Moreover,change the blocks...
...ZynQ SoC. Tool is Vivado 16.2 (SDK). At Ethernet interface (PS of ZynQ FPGA), mixed traffic is to be differentiated based on pre-defined IP and Ports and IP packets are to be routed to respective application. Rest all traffic (RAW Ethernet Frames) to be passed on to PL part (FPGA). This can be done by keeping Ethernet packets in DDR. And then AXI interface