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    System Verilog Project 5 6 days left
    VERIFIED

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $119 (Avg Bid)
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    13 bids

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $178 (Avg Bid)
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    17 bids

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
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    5 bids

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $110 (Avg Bid)
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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $133 (Avg Bid)
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    7 bids

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [login to view URL] Using PG236 [login to view URL]

    $128 (Avg Bid)
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    3 bids

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    $75 (Avg Bid)
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    1 bids

    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    $42 / hr (Avg Bid)
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    1 bids

    I need image encryption using verilog on FPGA board

    $811 (Avg Bid)
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    13 bids

    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

    $29 (Avg Bid)
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    16 bids

    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

    $563 (Avg Bid)
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    11 bids
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    1 bids

    Hi, I want a 2D convolution module in Verilog, using DSPs.

    $45 (Avg Bid)
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    8 bids
    Quartus Ended

    I need you to develop some software for me. I would like this software to be developed for Linux . Edit the code in FPGA Board of a printer written in Verilog language.

    $27 (Avg Bid)
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    I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd

    $113 (Avg Bid)
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    9 bids
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    I have a serial adder that I need converted to serial multiplier in system Verilog. very easy only 1 hour work

    $19 (Avg Bid)
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    7 bids

    i need a code for serial multiplier using verilog not from online please

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    Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...

    $112 (Avg Bid)
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    11 bids

    i need a verilog code for serial multipler

    $31 (Avg Bid)
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    Need help cleaning up some code, and matrix multiplication.

    $50 (Avg Bid)
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    I need Verilog Code for BMI calculation that can be running in Quartus software.

    $105 (Avg Bid)
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    3 bids

    I want someone to make a 40 minutes video to teach me how to Use cadence tool to synthesize digital circuit from Verilog code and simulation and do the static timing analysis and static power analysis in a given digital circuit which contains XORs and Multiplexers

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    We require a simple oscilloscope project to be implemented using only Verilog code on DE1-SoC board by the latest date of 7th of May as agreed during the chat conversation. This project will comprise of modular Verilog code, fully commented, test-benches for verification and a technical report of the project. Altera Quartus software will be used for

    $210 (Avg Bid)
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    1 bids

    A very simple oscilloscope developed using Verilog on Altera software, this project will be based on DE1-SoC Board and is expected to be concluded within a week. Only experienced FPGA engineers please.

    $226 (Avg Bid)
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    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

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    ...to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not quite sure with the Verilog language

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    ...hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language,OVM/UVM Methodology knowledge and experience

    $347 (Avg Bid)
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    3 bids

    Verilog code of Simplified DES algorithm

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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $283 (Avg Bid)
    $283 Avg Bid
    11 bids

    I need someone to help me modify a Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think t...any other sensors I haven't mentioned will work better? Therefore, I think we need some chat to find a solution before start working. FPGA: Xilinx Basys3 Language: Verilog HDL Software: Vivado 2015.4

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    6 bids

    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

    $158 (Avg Bid)
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    18 bids

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

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    10 bids
    200418_Verilog Ended
    VERIFIED

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    $50 - $80
    Sealed
    $50 - $80
    4 bids

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    $388 (Avg Bid)
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    6 bids

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

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    Tcp sending on FPGA using verilog xgmii xilinx vivado

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    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

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    5 bids

    more details will be given in the chat

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    15 bids

    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

    $77 (Avg Bid)
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    1 bids

    Small project on computer architecture

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    20 bids

    I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated

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    1 bids

    I need the design of a microprocessor with 16 cores and 16 bit data bus with basic MIPS ISA, with 4 stage pipeline. I need the verilog code, testbench and physical design layout and testing (I will provide Synopsys tools)

    $566 (Avg Bid)
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    ...Language=English&CategoryNo=167&No=921) and 2. wiz830mj ([login to view URL]). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog source code, which initializes W5300 chip and sends some data to PC by TCP/IP. The solution should be verified by sending ascending numbers from 0 to 255(8 bits) in an endless

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    I need Verilog hardware description language expert. I need to modify two modules only: mips.v and mips-control.v. Details are in the attached file.

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    7 bids

    MIPS and extend in Verilog and datapath for a single-cycle

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    Design a UART module to interface it with a PC

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