This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.
...software for me. I would like this software to be developed . You will have to program an FPGA card that I will provide, to work for crypto mining. I will provide the software that works under windows and Linux and you will have to make this software works with the FPGA that will provide to you. Software will have to be perfectly optimized. You will
Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position
I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url removed, login to view] Please respond directly with any questions such as specific mining software and such.
Help me to research and find a suitable FPGA board for my project.
traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)
I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware.
verilog code for SPI slave module
I want to develop a serial interface on my FPGA board, serial communication from host done by Python.
I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated
I need the design of a microprocessor with 16 cores and 16 bit data bus with basic MIPS ISA, with 4 stage pipeline. I need the verilog code, testbench and physical design layout and testing (I will provide Synopsys tools)
...simple: I send 31 bytes from my computer to the FPGA (through UART), the FPGA makes some calculations and then I receive 54 bytes back to my PC (through UART again). The problem is that, I'm not receiving what is expected according to the simulation. Moreover, everytime I send the same bytes to the FPGA, I get back a different answer (which is not possible)
...re-write the FPGA firmware to accommodate a faster ADC chip. We are currently using an 80 MSPS 14 bit ADC (AD9245BCPZ-80), which is the fastest in that specific form factor. Ideally, we would like to go as high as 180 MSPS whilst keeping the board the same size. This would require some re-work of the board and a re-writing of the FPGA code. We do
...direction data flow from FPGA to PC using: 1. Evaluation board Terasic DE0-CV ([url removed, login to view]) and 2. wiz830mj ([url removed, login to view]). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog source code, which initializes