Spi fpga vhdl verilog jobs

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    4,812 spi fpga vhdl verilog jobs found, pricing in USD

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

    $45 (Avg Bid)
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    PCBA (FPGA) board design 2 days left
    VERIFIED

    I need the design of PCBA/FPGA (Gerber file and BOM)

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    Following the sa...my categories to put inside my navigation menu on my ecommerce. The categories topics are: 1: Microcontrolers, Modules 2: Arduino, Raspberry pi, Tensilica, STM32, ATTINY, FPGA 3: Breadboard, Power Source, Network, Sensors, Modules, Relay (actuators), LED, CNC, Motor, USB, Memory, Infra-RED, Radio Frequency, Temperature, ASIC Chips

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    I am a cryptocurrency miner, and I would like to buy a larger number of FPGA cards to mine with, specifically the Xilinx VCU1525 FPGA Card. I need someone to Program the card to mine a number of specific algorithms. Preferably the dagger hashimoto, Neoscrypt, Equihash algorithms, I need a quote on how much this will cost.

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    i need vhdl project for fpga bord i need skeleton and can move

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    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

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    Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

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    ...computer is a windows 10 PC. Experience with Squid is needed. I have attached the relevant links so that you can gain a greater understanding [login to view URL] [login to view URL] The script should make it easy for me to enter: Import simple file with list of Server IP’s Username and password Date and Time

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    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

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    I am seeking for someone who is able to develop to connect SPI interface display module to Banana pi M2M referring at [login to view URL] and push notification for video door phone for android/ios mobile phone If you are interested in please contact me after this message.

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    Hello Freelancers! I have this project in C language for the end of month DESCRIPTION: I...potentiometer and will start at 1kHz. The type of filter will be determined by typing a button. I'm sending you a photo of the board with the dspic30f4012 microcontroller and the SPI MCP4921. Thank you in advance for your interest and time. Happy biding :)

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    We are seeking a consultant to migrate several Xilinx K7, K7 Ultra and/or V7 FPGA-based DSP Apps (developed using Vivado) to OpenCL so they can run on Intel, AMD/ATI, NVIDIA and mobile GPUs. Ideally, the OpenCL acceleration would fit into our existing Windows / LabVIEW framework so we could have compatibility with our current set of apps.

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    we sell our customers some IP (named CoaXPress FPGA IP). the price is one time however there is first year of maintenance and warranty provided free of cost with purchasing. Following years of maintenance are optional (not mandatory). However, if its not purchased, then customers will net get updates or support of their product. In case of requirement

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    I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP core to reduce the input board clock from 100 MHz down to 2 MHz which drives a Unique Chip ID core. It also blinks an LED on the board. You can download the project here:

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    i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you

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    I need you to implement a vcdl design project

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    Designing an FPGA board for "5CEFA9F27I7N altera cyclone v". A board that include 4 ram sockets, full-size DIMM (desktop pc ram), DDR3. And programming an FPGA crypto miner for this board.

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    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

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    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

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    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

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    I am looking someone who can fix the errors of the game tic tac toe in VHDL for DE2-115 and prepare report.

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    We are looking for a System Verilog Training for few Engineers in our premises.

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    I need you to develop some VHDL designs for me. I would like this software to be developed in VHDL hardware descriptive language. With a  VHDL design and simulation

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    ...Micro-controller through SPI. XMEGA A1U Micro-controller will be connected to two RF micro-controllers AX8052F100 that are connected to two transceivers one acts as transmitter and the other acts as a receiver. I need someone who can write a code on Atmel XMEGA A1U to do the following : Transmit mode: send data received from Arduino (SPI port 1) to the transmitter

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    Need help setting up (compiling) an Atmel Studio 7 example project for a different board than the expected. The project name is SPI_MASTER_BOOTLOADER. Changing from ...example project for a different board than the expected. The project name is SPI_MASTER_BOOTLOADER. Changing from the Atmel SAMD20 mcu to the SAMD21. Mapping to my boards SPI pins.

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    Need an SPI interface for an attiny84. It will be used to send an encoder count to the master on request. Intend to be compatible with SPI library for Arduino (which will be the master)

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    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

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    I am looking at an FPGA project using xilinx the project has very specific functions that i do not have the skills required to implement it myself sadly so i hope you can help with that. The project is for a crypto miner that can mine using the cryptonote algorithm Variant 1 i have chosen a model of FPGA as it has 100k logic gates and good memory

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    Hello I am doing a small project and am on the lookout for FPGA and software developer to work on a prototype. We are creating a product that is very similar to SmallHD monitors where we take a HDMI signal, process that signal and display that video signal plus overlays such as histograms, false colour and 3D LUTS. What we require for this prototype

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    I am in need of an FPGA programmer for a Xilinix FPGA which I plan to mine cryptocurrencies with. If you have knowledge in this field I hope to hear from you.

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    ...serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function)

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    ...serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function)

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    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

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    Hi, I want to implement a CNN in a Xilinx FPGA using Caffe or Tensorflow.

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    I am looking for a person who had experience on Instrument panel cluster. modules such as Ethernet,SPI and Line test and aging test.

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    ...freelancer to develop FPGA software alghorithm for Cryptonight V7 mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. Develop FPGA bitstream for mining Cryptonight v7 (CN7) algorithm on Xilinx Virtex UltraScale+ FPGA VCU1525 card + modify the miner software on PC to communicate with the FPGA. Miner software can communicate with FPGA card either ...

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    HDL coding from block diagram and pseudo algorithm

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    Need someone to do circuit design for an FPGA board. The board is being made from scratch. All we have so far is the FPGA chip.

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    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

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    ...battery power or capacitors (preferred). Upon +12V DC loss, the battery should power the Raspberry Pi for ~5 minutes and a signal should be sent to the Raspberry Pi over either an SPI or I2C interface to shutdown the Raspberry Pi. Within the same circuit, I'd also like to power an AV amplifier/distributor. The circuit should take one RCA input (Video, Left

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    The PONF Project ([login to view URL]) want to create ...looking for an engineer that helps us design the electronics to control the Sony sensors to be connected to the Raspberry PI at the core of the project. We will be using Lattice FPGA to convert data. The requirement is to design the electronics, the relative PCB and create relative documentation.

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    I am working on a nRF52 project where MPU-9250 is connected with i2c interface and (ssd1331) display will be connected via spi. Project Details Initial Setup: Once the device is connected, mobile will pass struct data to do initial set up. This data will be: • Name of device: 15 Chars long • Unique ID: A uuid • Current Time Device Name and

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    ...IAR Systems, Embedded Workbench from Texas Instruments (comes with ez430 USB KIT. Web site: [login to view URL]). I need to develop the interface (SPI Bus) from MSP430 Target Board to LSI_CSI 32-bit Quadrature Counter with serial interface ([login to view URL] ) . I will supply all hardware!

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    Develop a musical bell that will play a selected and programmed song in the FPGA.

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    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

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    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

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