Following the sa...my categories to put inside my navigation menu on my ecommerce. The categories topics are: 1: Microcontrolers, Modules 2: Arduino, Raspberry pi, Tensilica, STM32, ATTINY, FPGA 3: Breadboard, Power Source, Network, Sensors, Modules, Relay (actuators), LED, CNC, Motor, USB, Memory, Infra-RED, Radio Frequency, Temperature, ASIC Chips
I am a cryptocurrency miner, and I would like to buy a larger number of FPGA cards to mine with, specifically the Xilinx VCU1525 FPGA Card. I need someone to Program the card to mine a number of specific algorithms. Preferably the dagger hashimoto, Neoscrypt, Equihash algorithms, I need a quote on how much this will cost.
We are seeking a consultant to migrate several Xilinx K7, K7 Ultra and/or V7 FPGA-based DSP Apps (developed using Vivado) to OpenCL so they can run on Intel, AMD/ATI, NVIDIA and mobile GPUs. Ideally, the OpenCL acceleration would fit into our existing Windows / LabVIEW framework so we could have compatibility with our current set of apps.
we sell our customers some IP (named CoaXPress FPGA IP). the price is one time however there is first year of maintenance and warranty provided free of cost with purchasing. Following years of maintenance are optional (not mandatory). However, if its not purchased, then customers will net get updates or support of their product. In case of requirement
...very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP core to reduce the input board clock from 100 MHz down to 2 MHz which drives a Unique Chip ID core. It also blinks an LED on the board. You can download the project here: https://www
i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you
...Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period is not wired up in the DE0-CV board) o Hours will be displayed in “military time” (meaning 00 through 23)
I am looking at an FPGA project using xilinx the project has very specific functions that i do not have the skills required to implement it myself sadly so i hope you can help with that. The project is for a crypto miner that can mine using the cryptonote algorithm Variant 1 i have chosen a model of FPGA as it has 100k logic gates and good memory
Hello I am doing a small project and am on the lookout for FPGA and software developer to work on a prototype. We are creating a product that is very similar to SmallHD monitors where we take a HDMI signal, process that signal and display that video signal plus overlays such as histograms, false colour and 3D LUTS. What we require for this prototype
...description of my project and please only serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation
firstly i am posting this second time because the guy called https://www.freelancer.com/u/ahmedmohamed85?ref_project_id=17168255 (Ahmedmohamed85) has showed is arrogance and negligence after accepting my project and asked me to create a milestone and cancelled it and made me to wait for 3 days without answering please guys kindly dont get fooled with
...freelancer to develop FPGA software alghorithm for Cryptonight V7 mining using Xilinx Virtex UltraScale+ FPGA VCU1525 card. Develop FPGA bitstream for mining Cryptonight v7 (CN7) algorithm on Xilinx Virtex UltraScale+ FPGA VCU1525 card + modify the miner software on PC to communicate with the FPGA. Miner software can communicate with FPGA card either ...
The PONF Project ([login to view URL]) want to create a modular camera that bring together in a seamless, easy workflow photography and IoT. Ours is a (partially) Open Source project, and we hope to involve engineers that may want to help us making the whole camera. We are looking for an engineer that helps us design the electronics to control the Sony
...template project which allows me to transfer about 2kB of settings from the HPS side to the FPGA side. I want to use C on the HPS side to set 2048x 8-bit values which the FPGA can use to synthesize an arbitrary waveform in real-time. The memory can be SDRAM or any other suitable options available on the DE1-SoC board. The template project should include
Looking for a embedded Linux developer/engineer for developing a driver for an iMX6 module on a custom board for capturing 16-bit greyscale video supplied by an FPGA through the camera sensor interface on the IPU of the microprocessor. Must have previous experience with IPU drivers and camera interfacing, as well as driver development for embedded Linux
i am FPGA fan and , I try to setup connection between fpga device ( NetFPGA-1G-CML Kintex-7 ) and local computer . My main objective : simple comunication over ethernet cable . I have already done hardware design (in vivado) - microblaze core + TEMAC ([login to view URL]), which is verifed and works
...amplifier (hence 6 amplifiers circuits). The output of the 6 amplifiers will go into 3 dual ADC's. The ADC will then send signal to connectors will an FPGA card will plug into. There is a signal from the FPGA that is sent to a DAC. I am basically designing a IO carrier board based on the ZED board (see attached) I can only work with US citizens since
1. Create a top level VHDL file for the project. VHDL code should be well formatted and commented. 2. Add two instantiations of a sync counter to the top level that are customized for the horizontal and vertical sync signals 3. Adapt the tesbench from homework 2 to simulate the top level file. Simulations should be annotated to depict events important
Develop and deliver FPGA code in vivado to: Take in attached NOAA wave file (IQ based) and decode it into a weather satellite image. This wave file was a recording of from NOAA satellite's Automatic Picture Transmission. The signal itself is a 256-level amplitude modulated 2400Hz subcarrier, which is then frequency modulated onto the 137 MHz-band
Designing of a pipeline processor which uses RISC like instruction set And implementation on fpga
I have to do video compression using FPGA(Field Programmable Gate Array) for a video recorder..
...is already able to take pictures. We need a Zynq developer to write FPGA code that will process the pictures. We're using the Zynq 7010 clg225: [login to view URL] Specifically, we want streaming FPGA code that will: 1. Subtract the median-filtered image from the original
The purpose of this lab is to design a VGA driver to display 256 different colors on a monitor. Two timing signals are generated in this system, vsync an...synchronization signals are generated. This way, as the counter counts, 256 different color combinations are displayed on the screen one after another. This counter is implemented on the FPGA board
in the project there is a basic game. There are some walls placed vertically and an object slides and try to avoid crash these walls by using up and down buttons on FPGA. it is not mandatory to be a complex project. I need to have in a week.
Hi Chris, I saw a message stating you had experience creating a FPGA miner. I am trying to learn how to program FPGA and wanted to start with making a crypto miner so I can try to pay off the hardware. I am willing to pay to get some assistance and pointers and any example projects you are willing to share. My hardware is Xilinx AVNET VCU-1525 development
I need someone who can run digital electronic simulation with Intel/Altera Quartus II v15.0 ( I will provide that) and then implement the simulations on FPGA-Based Digital Circuit: Rainbow RGB LED Driver. Please only contact me if you are 100% capable of the above. I can provide the software but You need to have the equipment.
BId only if u can do only the second Part for $50 and within 3 days stereoscopic vision system the aim stereo vision uses two adjacent cameras to creat a 3d image of the world . A depth map can be created by comparing the offset of the corresponding pixels from the two [login to view URL] for real time stereo vision the image data needs to be processed