Image steganography implemented fpga using verilog jobs

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    3,634 image steganography implemented fpga using verilog jobs found, pricing in USD
    FPGA TCPIP implementation 6 days left
    VERIFIED

    FPGA TCPIP implementation using Verilog

    $21 / hr (Avg Bid)
    $21 / hr Avg Bid
    8 bids

    We have an almost complete aut...cRIO We need someone to make minor modifications and possibly offer ongoing support in the future. You should be familiar with LabVIEW coding for cRIO including the internal FPGA We are based just south of Milton Keynes, if this is of interest please call [Removed by Freelancer.com Admin] to discuss further details

    $39 / hr (Avg Bid)
    Local
    $39 / hr Avg Bid
    1 bids

    We need to connect Sony imaging sensors (not industrial ones) to Raspberry PI, using Lattice FPGA. We are looking for expert designers, with their own design tools. We only need the design of the electronics, so no physical tests, and no components available. The design will be checked for compliance before final payment. Possible further cooperation

    $372 (Avg Bid)
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    13 bids
    Networking Based Project 3 days left
    VERIFIED

    Combined Technique of Cryptography and Steganography.

    $124 (Avg Bid)
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    16 bids

    I am looking for people who join my team, we are working with new FPGA miner which are highly efficient that everybody can profit. basically it is a binary salery plan with a crypto mining product. So you have the chance to start your own business in the field or you work for me as a freelancer and get for every customer that signs up a reward of 25

    $35 - $292
    $35 - $292
    0 bids

    Verilog digital logic deisgn simple work

    $23 (Avg Bid)
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    18 bids

    ...belongs to steganography concept . I want java source code for two algorithms that i mentioned in below abstract . Basically we are doing comparative study on three algorithms to find best algorithm based on the criteria like time complexity and space complexity. we have already java source code for one algorithm (TEXT STEGANOGRAPHY BY CHANGING

    $21 (Avg Bid)
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    2 bids
    steganography 1 day left

    ...belongs to steganography concept . I want java source code for two algorithms that i mentioned in below abstract . Basically we are doing comparative study on three algorithms to find best algorithm based on the criteria like time complexity and space complexity. we have already java source code for one algorithm (TEXT STEGANOGRAPHY BY CHANGING

    $65 (Avg Bid)
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    2 bids

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

    $46 (Avg Bid)
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    16 bids

    I need the design of PCBA/FPGA (Gerber file and BOM)

    $691 (Avg Bid)
    $691 Avg Bid
    25 bids

    Following the sa...my categories to put inside my navigation menu on my ecommerce. The categories topics are: 1: Microcontrolers, Modules 2: Arduino, Raspberry pi, Tensilica, STM32, ATTINY, FPGA 3: Breadboard, Power Source, Network, Sensors, Modules, Relay (actuators), LED, CNC, Motor, USB, Memory, Infra-RED, Radio Frequency, Temperature, ASIC Chips

    $117 (Avg Bid)
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    28 bids

    F5 algorithm is available on github for jpeg image. You have to re-implement it for video instead of LSB substituition, with some more functionalities(see attached file). GUI would be nice and any programming language can be used. You have to make document/comments to make the code and algorithm understandable to me. Have to get some steganalysis results

    $119 (Avg Bid)
    $119 Avg Bid
    9 bids

    I am a cryptocurrency miner, and I would like to buy a larger number of FPGA cards to mine with, specifically the Xilinx VCU1525 FPGA Card. I need someone to Program the card to mine a number of specific algorithms. Preferably the dagger hashimoto, Neoscrypt, Equihash algorithms, I need a quote on how much this will cost.

    $16947 (Avg Bid)
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    11 bids

    i need vhdl project for fpga bord i need skeleton and can move

    $24 (Avg Bid)
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    14 bids

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    $23 (Avg Bid)
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    22 bids

    Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

    $220 (Avg Bid)
    $220 Avg Bid
    14 bids

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    $22 (Avg Bid)
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    17 bids

    We are seeking a consultant to migrate several Xilinx K7, K7 Ultra and/or V7 FPGA-based DSP Apps (developed using Vivado) to OpenCL so they can run on Intel, AMD/ATI, NVIDIA and mobile GPUs. Ideally, the OpenCL acceleration would fit into our existing Windows / LabVIEW framework so we could have compatibility with our current set of apps.

    $9212 (Avg Bid)
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    we sell our customers some IP (named CoaXPress FPGA IP). the price is one time however there is first year of maintenance and warranty provided free of cost with purchasing. Following years of maintenance are optional (not mandatory). However, if its not purchased, then customers will net get updates or support of their product. In case of requirement

    $125 (Avg Bid)
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    31 bids

    I have a very simple FPGA project to test the Intel Arria 10 SoC Dev kit (DK-SOC-10AS066S-A) with Quartus Prime Pro 18.0 as follows. The main code instantiates an IOPLL Intel FPGA IP core to reduce the input board clock from 100 MHz down to 2 MHz which drives a Unique Chip ID core. It also blinks an LED on the board. You can download the project here:

    $106 (Avg Bid)
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    5 bids

    i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you

    $37 (Avg Bid)
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    6 bids

    Designing an FPGA board for "5CEFA9F27I7N altera cyclone v". A board that include 4 ram sockets, full-size DIMM (desktop pc ram), DDR3. And programming an FPGA crypto miner for this board.

    $3000 - $5000
    $3000 - $5000
    0 bids

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    $21 / hr (Avg Bid)
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    20 bids

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    $131 (Avg Bid)
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    19 bids

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
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    Looking for an enterprise architect who can create design document for the already existing systems in a bank. The requirement is that he/she has the knowledge to create the HLD,LLD and application flows after discussion with the client. There is no documentation present at the moment and all the information has to be gathered from the client and has to be detailed in a High level and low level do...

    $8292 (Avg Bid)
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    We are looking for a System Verilog Training for few Engineers in our premises.

    $1983 (Avg Bid)
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    I'm looking for someone who would be able to implement some code in Python. I have a header I need it to be in as it needs to be generated each request. the header would look like so: "myhead={'Accept':'*/*', 'X-Platform':'android', 'X-Language':'en', 'Content-Type':'application/json', '...

    $45 (Avg Bid)
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    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    $100 (Avg Bid)
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    8 bids

    I am looking at an FPGA project using xilinx the project has very specific functions that i do not have the skills required to implement it myself sadly so i hope you can help with that. The project is for a crypto miner that can mine using the cryptonote algorithm Variant 1 i have chosen a model of FPGA as it has 100k logic gates and good memory

    $366 (Avg Bid)
    $366 Avg Bid
    9 bids

    Hello I am doing a small project and am on the lookout for FPGA and software developer to work on a prototype. We are creating a product that is very similar to SmallHD monitors where we take a HDMI signal, process that signal and display that video signal plus overlays such as histograms, false colour and 3D LUTS. What we require for this prototype

    $830 (Avg Bid)
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    6 bids

    I am in need of an FPGA programmer for a Xilinix FPGA which I plan to mine cryptocurrencies with. If you have knowledge in this field I hope to hear from you.

    $607 (Avg Bid)
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    12 bids

    ...serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function)

    $366 (Avg Bid)
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    2 bids

    ...serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e PT1 transfer function)

    $58 - $140 / hr
    $58 - $140 / hr
    0 bids

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $123 (Avg Bid)
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    20 bids

    Hi, I want to implement a CNN in a Xilinx FPGA using Caffe or Tensorflow.

    $247 (Avg Bid)
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    2 bids

    Need someone to do circuit design for an FPGA board. The board is being made from scratch. All we have so far is the FPGA chip.

    $250 - $750
    Sealed
    $250 - $750
    7 bids

    Hello! We have to do some fixes on a tomcat 9 steganography project. These fixes have to be done in 5-6 days fron now and budget is aprox $60-80 USD. The full description is in the ATTACHED doc file. The oproject is here: [login to view URL] (you just need to change the paths) I also ATTACH the flow and a video whose purpose is explained

    $132 (Avg Bid)
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    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $184 (Avg Bid)
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    15 bids

    I have an SMM panel which runs off of the Twig Framework. It has template files in place (see pictures). I have my own HTML/CSS/JS Template I would like integrated into this. (see pictures) Sections I need completed are: - All Pages to have the basic design in place (Background/Header/Design colour) - Main page to have full template design in place (from pictures) and to have a login box create...

    $107 (Avg Bid)
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    Develop a musical bell that will play a selected and programmed song in the FPGA.

    $86 (Avg Bid)
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    In this task, it's required to use use threads and mutexes from the pthreads library. We previously had the same dining philosophers problem which we were required o solve using processes and semaphores. I attached this one as well in case it helps. Deadline, it was today, sadly I wasn't able to submit anything. So the sooner you can finish it the

    $35 (Avg Bid)
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    1 bids

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
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    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $106 (Avg Bid)
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    ...DE1-SoC developmental board and I need a template project which allows me to transfer about 2kB of settings from the HPS side to the FPGA side. I want to use C on the HPS side to set 2048x 8-bit values which the FPGA can use to synthesize an arbitrary waveform in real-time. The memory can be SDRAM or any other suitable options available on the DE1-SoC

    $139 (Avg Bid)
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    7 bids

    control a sensorless bldc motor using fpga

    $19 / hr (Avg Bid)
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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object...have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $132 (Avg Bid)
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    Mining Mining Mining Mining Mining Mining

    $594 (Avg Bid)
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