Image steganography implemented fpga using verilog jobs

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    3,545 image steganography implemented fpga using verilog jobs found, pricing in USD
    $23 Avg Bid
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    ...to do Verilog codes on Fast Fourier Transform processor for both Radix-2 and Radix-4 of 8-bit by using Xilinx software. I need to get the test values design along with its output waveforms. I am working on a project of 'Design and Simulation of a Fast Fourier Transform Processor using Verilog'. However, I am not quite sure with the Verilog languag...

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    ...hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog, System Verilog or SystemC Experience of working on Functional Verification, SoC Verification, Emulation Good in programming : System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language,OVM/UVM Methodology knowledge and experience

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    Verilog coding 5 days left

    Verilog code of Simplified DES algorithm

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    Hello I am looking for some to build and cusotmize the opencl FPGA based on AMD etc. Especially you have rich experience with FPGA network communication.. Please send me message if you are ready with this project.

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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object...have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

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    ...Demo(FPGA: Xilinx Basys3 Language:Verilog) which is a object tracking system based on a pan-tilt. I think the modification won't be a big task, because the imaging processing algorithm works well, the need of modification is in controling two servos, especilly in getting back servos' position. The original demo get servos' position by using four

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    программа должна быть похожа как на этом сайте: [url removed, login to view] ТЗ прикрепленное the program should be similar to this site: [url removed, login to view] TZ attached

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    CAMERA ITS 3 days left

    ...needs to be Global Shutter. The camera will operate in snapshot mode, taking an on-demand image of an external trigger. (max 2 frames per second) It should have a good quality board bayer interpolation, either using a dedicated Image Signal Processor or an FPGA. Must send data through a digital data bus such as RGB or YUV (preferred RGB) The camera

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    ...infographic sections to be updated. There are drawings which show the services we provide as a business. When someone hovers their mouse over a certain part of the image, the rest of the image darkens and the relevant section that is highlighted will show text about what we do. You need to have relevant experience doing this and be able to show examples

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    Hi there Please check the document

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    FPGA Design 1 day left

    Hi there Please check the document!

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    Board : Terasic DE10-Lite MAX10 10M50DAF484C7G - 2 push buttons - 10 switches - 6 7-segments - 1 SDRAM module (ISSI IS4216320D) - see [url removed, login to view] for more details about the board Software tool : Altera / Intel Quartus Prime Lite 16.1 Project : create a small, minimalistic, Quartus project to illustrate the use of PLL ...

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    I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL

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    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

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    200418_Verilog 13h left
    VERIFIED

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

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    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    $388 (Avg Bid)
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    This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety

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    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

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    [url removed, login to view]://[url removed, login to view]%252091.pdf&ved=2ahUKEwjKmeiMk8faAhVFMY...implement the project. Everything is mentioned clearly in it. I want this project before Saturday morning. So the final system should detect faces present in an image implement ed using system generator.

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    Tcp sending on FPGA using verilog xgmii xilinx vivado

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    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

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    ...software for me. I would like this software to be developed . You will have to program an FPGA card that I will provide, to work for crypto mining. I will provide the software that works under windows and Linux and you will have to make this software works with the FPGA that will provide to you. Software will have to be perfectly optimized. You will

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    more details will be given in the chat

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    Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position

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    I need an iPhone/iPad app. I already have a design for it, I just need it to be built. I have a freelancer working for me and I want to hire another person to work with him. Freelancer with more than 2 years of experience in IOS development will be preferred. This budget is not exactly correct and I require a developer urgently.

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    I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url removed, login to view] Please respond directly with any questions such as specific mining software and such.

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    Help me to research and find a suitable FPGA board for my project.

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    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

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    I want to get a simple 3 layer (Inp...layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware.

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    We are small non-proft. We would like to migrate from civicrm to salesforce.com. This will involve exporting data( very small) from civicrm (CSV), implement donation module and a membership module. must have worked with sales force

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    Details later.. I will check your BASIC.. And then recruit You

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    Program a FPGA to work as a MC6803 on a device like a Digilent Cmod A7: Breadboardable Artix-7 FPGA Module. [url removed, login to view] . will need relevant information to program multiple devices.

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    We want to have a linear program which compares product prices of ca. 50 different products from ca. 6 different companies and returns the value of the lowest company including the company name. We already have a database with products including prices. The search fields and results must eventually be shown on a website.

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    Small project on computer architecture

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    I want to develop a serial interface on my FPGA board, serial communication from host done by Python.

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    I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated

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    I need the design of a microprocessor with 16 cores and 16 bit data bus with basic MIPS ISA, with 4 stage pipeline. I need the verilog code, testbench and physical design layout and testing (I will provide Synopsys tools)

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    ...simple: I send 31 bytes from my computer to the FPGA (through UART), the FPGA makes some calculations and then I receive 54 bytes back to my PC (through UART again). The problem is that, I'm not receiving what is expected according to the simulation. Moreover, everytime I send the same bytes to the FPGA, I get back a different answer (which is not possible)

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    ...re-write the FPGA firmware to accommodate a faster ADC chip. We are currently using an 80 MSPS 14 bit ADC (AD9245BCPZ-80), which is the fastest in that specific form factor. Ideally, we would like to go as high as 180 MSPS whilst keeping the board the same size. This would require some re-work of the board and a re-writing of the FPGA code. We do

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    Design a serial interface using Python for communication with FPGA.

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    ...direction data flow from FPGA to PC using: 1. Evaluation board Terasic DE0-CV ([url removed, login to view]) and 2. wiz830mj ([url removed, login to view]). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog source code, which initializes

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    i want a ja...want a java program to hide text in an image using LSB and decrypt the text using MD5 the program WITHOUT interface the program works as follows: encrypt function takes a string and encrypted using MD5 and hiding it in an image. decrypt function takes an image and return the hidden text that decrypted using MD5 and decrypt i...

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    ...细节是用GPIO模仿Jtag烧录两片Xilinx的PROM. (XCF04S, XCF01S). Xilin有比较详细的方案。 见副件。 如果你们承接这类工程, 请你给我一个报价。 我们有硬件平台, 你们需要提供, 1 windows usb 的驱动, 指定等待下载的文件。 Cy7c68013A 的程序,把指定的文件烧录到目标PROM. 启动系统, 读取FPGA内部寄存器,确定烧录成功。

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    I am looking for someone that can program or port an existing Windows or Linux mining program for AMD GPU's to a Xilinx Kintex-7 FPGA I will provide details and Github privately

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    I need Verilog hardware description language expert. I need to modify two modules only: mips.v and mips-control.v. Details are in the attached file.

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    MIPS and extend in Verilog and datapath for a single-cycle

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